| /openjdk7/hotspot/src/cpu/sparc/vm/ |
| H A D | sharedRuntime_sparc.cpp | 178 __ stx(G1, SP, g1_offset+STACK_BIAS);
179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
238 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
239 __ wrccr (G1) ;
245 __ ldx(SP, g1_offset+STACK_BIAS, G1);
293 // 32bit build returns longs in G1
294 __ ldx(SP, g1_offset+STACK_BIAS, G1);
536 // G1: 1st Long arg (32bit build)
546 __ mov(G1, L
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| H A D | register_sparc.hpp | 120 CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1));
175 #define G1 ((Register)(G1_RegisterEnumValue)) macro
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| H A D | assembler_sparc.cpp | 210 add( G0, G1, G2 );
261 udiv( G0, (1 << 12) - 1, G1 );
262 sdiv( G1, G2, G3 );
326 ldsh( G1, G3, G4 );
335 lduw( G1, -1, G2 );
355 ldda( G0, G1, 4, G2 );
429 popc( G0, G1);
514 swapa( G0, G1, 13, G2 );
527 trap( overflowClear, xcc, G0, G1 );
561 stdc( 1, G1,
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| H A D | register_definitions_sparc.cpp | 37 REGISTER_DEFINITION(Register, G1);
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| H A D | cppInterpreter_sparc.cpp | 188 // longs in G1 in the 32-bit build whereas the interpreter wants them in O0/O1.
189 // Since the interpreter will return longs in G1 and O0/O1 in the 32bit
192 // Note: I tried to make c2 return longs in O0/O1 and G1 so we wouldn't have to
195 __ stx(G1, L1_scratch, -wordSize);
346 // C2 expects long results in G1 we can't tell if we're returning to interpreted
347 // or compiled so just be safe use G1 and O0/O1
349 // Shift bits into high (msb) of G1
350 __ sllx(Otos_l1->after_save(), 32, G1);
353 __ or3 (Otos_l2->after_save(), G1, G1);
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| H A D | methodHandles_sparc.cpp | 578 __ mov(G1, L1);
586 __ mov(L1, G1);
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| H A D | templateInterpreter_sparc.cpp | 164 // longs in G1 in the 32-bit build whereas the interpreter wants them in O0/O1.
165 // Since the interpreter will return longs in G1 and O0/O1 in the 32bit
168 // Note: I tried to make c2 return longs in O0/O1 and G1 so we wouldn't have to
173 __ srl (G1, 0, O1);
174 __ srlx(G1, 32, O0);
648 // delay slot and damages G1
740 // 1. The "intrinsified" code for G1 (or any SATB based GC),
744 // * In the G1 code we do not check whether we need to block for
745 // a safepoint. If G1 is enabled then we must execute the specialized
750 // G1 pr
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| H A D | c1_LIRAssembler_sparc.cpp | 1557 // Must move the result to G1
1558 // Must leave proper result in O0,O1 and G1 (TIERED only)
1559 __ sllx(I0, 32, G1); // Shift bits into high G1
1561 __ or3 (I1, G1, G1); // OR 64 bits into G1
2103 __ inc_counter(counter, G1, G3);
2197 assert_different_registers(tmp, tmp2, G3, G1);
2200 __ load_klass(dst, G1);
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| H A D | c1_MacroAssembler_sparc.cpp | 320 assert(t1 == G1, "must be G1");
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| H A D | assembler_sparc.inline.hpp | 126 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
127 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
270 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
271 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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| H A D | interp_masm_sparc.cpp | 1148 // C2 expects long results in G1 we can't tell if we're returning to interpreted
1149 // or compiled so just be safe use G1 and O0/O1
1151 // Shift bits into high (msb) of G1
1152 sllx(Otos_l1->after_save(), 32, G1);
1155 or3 (Otos_l2->after_save(), G1, G1);
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| H A D | assembler_sparc.hpp | 81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
2344 // General G1 pre-barrier generator.
2347 // General G1 post-barrier generator
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| /openjdk7/jdk/src/share/classes/sun/nio/cs/ext/ |
| H A D | IBM33722.java | 109 private final int G1 = 1; field in class:IBM33722.Decoder
169 } else { // G1
230 } else { // G1
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