Searched defs:reg_offset (Results 1 - 19 of 19) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_power.c64 u32_t reg_offset = 0 ; local
161 reg_offset = ( offset / 8 ) - 1 ; // 0 - 15
162 val = (reg_offset*sizeof(u64_t)) ;
H A Dlm_hw_attn.c205 u32_t reg_offset; /* the register offset */ member in struct:_block_mask_info_t
440 offset = init_mask_values_arr[mask_idx].reg_offset;
H A Dlm_hw_access.c1393 u32_t reg_offset = 0; local
1424 reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM: NIG_REG_LLH0_FUNC_MEM) + 8*offset;
1428 reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2: NIG_REG_P0_LLH_FUNC_MEM2) + 8*(offset - MAX_OFFSET_IN_MEM_1);
1434 REG_WR_DMAE_LEN(pdev, reg_offset, wb_data, ARRSIZE(wb_data));
1443 reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM_ENABLE : NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*offset;
1447 reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE : NIG_REG_P0_LLH_FUNC_MEM2_ENABLE) + 4*(offset - MAX_OFFSET_IN_MEM_1);
1449 REG_WR(pdev, reg_offset, enable_mac);
1636 u32_t reg_wait_verify_val(struct _lm_device_t * pdev, u32_t reg_offset, u32_t excpected_val, u32_t total_wait_time_ms ) argument
1645 val=REG_RD(pdev,reg_offset);
1649 val=REG_RD(pdev,reg_offset);
1817 lm_reg_rd_blk( lm_device_t *pdev, u32_t reg_offset, u32_t *buf_ptr, u32_t u32t_cnt) argument
1839 lm_reg_rd_blk_ind( lm_device_t *pdev, u32_t reg_offset, u32_t *buf_ptr, u32_t u32t_cnt, u8_t acquire_lock_flag) argument
1870 lm_reg_wr_blk( lm_device_t *pdev, u32_t reg_offset, u32_t *data_ptr, u32_t u32t_cnt) argument
1893 lm_reg_wr_blk_ind( lm_device_t *pdev, u32_t reg_offset, u32_t *data_ptr, u32_t u32t_cnt) argument
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/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Despi.c50 int ch_addr, int reg_offset, u32 wr_data)
55 V_REGISTER_OFFSET(reg_offset) |
72 int ch_addr, int reg_offset, u8 *rd_data)
78 V_REGISTER_OFFSET(reg_offset) |
49 tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, int ch_addr, int reg_offset, u32 wr_data) argument
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dpic16f747.h109 uint8_t reg_offset; /* indirect register offset */ member in struct:minor_node_info
/illumos-gate/usr/src/uts/sun4u/io/i2c/clients/
H A Dpca9556.c183 int reg_offset, num_of_ports; local
203 reg_offset = 2;
206 reg_offset = 1;
235 reg = reg + reg_offset;
420 int reg_offset, num_of_ports; local
445 reg_offset = 2;
448 reg_offset = 1;
500 reg = reg + reg_offset;
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_mbx.c597 u32 reg_offset = (vf_number < 32) ? 0 : 1; local
606 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
611 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
619 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
/illumos-gate/usr/src/cmd/fm/modules/common/fabric-xlate/
H A Dfabric-xlate.h140 uint32_t reg_offset; /* sts reg for ereport table offset */ member in struct:fab_err_tbl
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hw.c879 uint64_t reg_offset; local
889 reg_offset = reg_base + DMC_OFFSET(channel);
890 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data);
900 uint64_t reg_offset; local
910 reg_offset = reg_base + DMC_OFFSET(channel);
914 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset));
/illumos-gate/usr/src/uts/sun4u/daktari/io/
H A Dhpc3130_dak.c763 char *reg_offset; local
876 reg_offset = s;
884 j = hpc3130_atoi(reg_offset);
914 hpc3130_atoi(reg_offset);
932 ste->callback_info.offset = hpc3130_atoi(reg_offset);
/illumos-gate/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_vgatext.c331 off_t reg_offset; local
370 &reg_offset);
392 &reg_offset);
421 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE,
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_82575.c2277 u32 reg_val, reg_offset; local
2281 reg_offset = E1000_DTXSWC;
2285 reg_offset = E1000_TXSWC;
2291 reg_val = E1000_READ_REG(hw, reg_offset);
2303 E1000_WRITE_REG(hw, reg_offset, reg_val);
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c203 uint_t reg_offset);
3503 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) argument
3539 reg_offset);
3541 if (reg_offset == PCI_CONF_ROM) {
/illumos-gate/usr/src/uts/intel/io/vgatext/
H A Dvgatext.c441 off_t reg_offset; local
491 &reg_offset);
511 &reg_offset);
539 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE,
/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_main.c250 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val) argument
256 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val);
260 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val);
265 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset) argument
272 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)));
276 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)));
/illumos-gate/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c3003 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) argument
3039 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3041 if (reg_offset == PCI_CONF_ROM) {
3070 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size);
3085 uint32_t base, uint32_t base_hi, uint_t reg_offset)
3118 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3122 if (reg_offset == PCI_CONF_ROM) {
3152 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size);
3084 pcicfg_update_assigned_prop_value(dev_info_t *dip, uint32_t size, uint32_t base, uint32_t base_hi, uint_t reg_offset) argument
/illumos-gate/usr/src/uts/sun4/io/
H A Dpcicfg.c3178 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) argument
3214 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3216 if (reg_offset == PCI_CONF_ROM) {
3305 uint32_t base, uint32_t base_hi, uint_t reg_offset)
3338 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3342 if (reg_offset == PCI_CONF_ROM) {
3373 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size);
3304 pcicfg_update_assigned_prop_value(dev_info_t *dip, uint32_t size, uint32_t base, uint32_t base_hi, uint_t reg_offset) argument
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_sp_verbs.c1095 u32 reg_offset = PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM : local
1109 reg_offset += 8*index;
1115 REG_WR_DMAE_LEN(pdev, reg_offset, wb_data, 2);
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h4081 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) argument
4084 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val);
4130 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) argument
4134 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val);
4135 LOG_REG_RD(pdev, (reg_offset), val);
4142 static __inline u32_t _vf_reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) argument
4145 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val);
4146 LOG_REG_RD(pdev, (reg_offset), val);
4171 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) argument
4175 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset,
4183 _vf_reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) argument
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