4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * CDDL HEADER START
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * The contents of this file are subject to the terms of the
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * Common Development and Distribution License (the "License").
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * You may not use this file except in compliance with the License.
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * See the License for the specific language governing permissions
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * and limitations under the License.
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * When distributing Covered Code, include this CDDL HEADER in each
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * If applicable, add the following below this CDDL HEADER, with the
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * fields enclosed by brackets "[]" replaced with your own identifying
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * information: Portions Copyright [yyyy] [name of copyright owner]
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * CDDL HEADER END
4f764f916501bcb9d3233dc547db1928fc2f22acCheng Sean Ye * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern "C" {
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu#define STRCMP(s1, s2) (strcmp((const char *)s1, (const char *)s2) == 0)
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * These values are used for the xxx_tgt_trans value in fab_data_t. They are
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * originally set in pcie_fault.c and originally defined in pcie_impl.h.
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern fmd_xprt_t *fab_fmd_xprt; /* FMD transport layer handle */
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern char fab_buf[];
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* PCI-E config space data for error handling and fabric ereports */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Original ereport NVL */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Device Information */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Ereport Information */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Error Registers */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pci_bdg_ctrl; /* PCI bridge control reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_bdg_stat; /* pcix bridge status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcix_ecc_control_0; /* pcix ecc control status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcix_ecc_status_0; /* pcix ecc control status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_fst_addr_0; /* pcix ecc first address reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_sec_addr_0; /* pcix ecc second address reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_attr_0; /* pcix ecc attributes reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcix_ecc_control_1; /* pcix ecc control status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcix_ecc_status_1; /* pcix ecc control status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_fst_addr_1; /* pcix ecc first address reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_sec_addr_1; /* pcix ecc second address reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcix_ecc_attr_1; /* pcix ecc attributes reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcie_err_status; /* pcie device status register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcie_err_ctl; /* pcie error control register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_dev_cap; /* pcie device capabilities register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_adv_ctl; /* pcie advanced control reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ue_status; /* pcie ue error status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ue_mask; /* pcie ue error mask reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ue_sev; /* pcie ue error severity reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ce_status; /* pcie ce error status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ce_mask; /* pcie ce error mask reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from SAER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu boolean_t pcie_ue_no_tgt_erpt; /* Don't send target ereports */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_status; /* pcie bridge secondary ue status */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_sue_tgt_trans; /* Fault trans type from AER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint64_t pcie_sue_tgt_addr; /* Fault addr from AER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_rp_status; /* root complex status register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcie_rp_ctl; /* root complex control register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_rp_err_status; /* pcie root complex error status reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */
036ec191c83e34650be17cd0fd75e7800aa95d35Cheng Sean Ye boolean_t pcie_rp_send_all; /* need to send ereports on all rps */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Pointer to function that prepares the ereport body */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t reg_offset; /* sts reg for ereport table offset */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu uint32_t reg_size; /* size of the status register */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu /* Pointer to function that prepares the ereport body */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu int (*fab_prep)(fmd_hdl_t *, fab_data_t *, nvlist_t *,
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Main functions for converting "fabric" ereports */
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_xlate_pcie_erpts(fmd_hdl_t *, fab_data_t *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_xlate_fabric_erpts(fmd_hdl_t *, nvlist_t *, const char *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_xlate_fire_erpts(fmd_hdl_t *, nvlist_t *, const char *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_xlate_epkt_erpts(fmd_hdl_t *, nvlist_t *, const char *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Common functions for sending translated ereports */
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern int fab_prep_basic_erpt(fmd_hdl_t *, nvlist_t *, nvlist_t *, boolean_t);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_send_tgt_erpt(fmd_hdl_t *, fab_data_t *, const char *,
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_send_erpt(fmd_hdl_t *hdl, fab_data_t *data, fab_err_tbl_t *tbl);
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Misc Functions */
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern void fab_pr(fmd_hdl_t *, fmd_event_t *, nvlist_t *);
036ec191c83e34650be17cd0fd75e7800aa95d35Cheng Sean Yeextern boolean_t fab_get_hcpath(fmd_hdl_t *, nvlist_t *, char **, size_t *);
036ec191c83e34650be17cd0fd75e7800aa95d35Cheng Sean Yeextern boolean_t fab_get_rcpath(fmd_hdl_t *, nvlist_t *, char *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern char *fab_find_rppath_by_df(fmd_hdl_t *, nvlist_t *, uint8_t);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern char *fab_find_rppath_by_devbdf(fmd_hdl_t *, nvlist_t *, pcie_req_id_t);
4f764f916501bcb9d3233dc547db1928fc2f22acCheng Sean Yeextern char *fab_find_rppath_by_devpath(fmd_hdl_t *, const char *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern char *fab_find_addr(fmd_hdl_t *hdl, nvlist_t *nvl, uint64_t addr);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern char *fab_find_bdf(fmd_hdl_t *hdl, nvlist_t *nvl, pcie_req_id_t bdf);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern boolean_t fab_hc2dev(fmd_hdl_t *, const char *, char **);
4df55fde49134f9735f84011f23a767c75e393c7Janie Luextern boolean_t fab_hc2dev_nvl(fmd_hdl_t *, nvlist_t *, char **);
036ec191c83e34650be17cd0fd75e7800aa95d35Cheng Sean Yeextern void fab_send_erpt_all_rps(fmd_hdl_t *, nvlist_t *);
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu#endif /* _FABRIC_XLATE_H */