Searched defs:reg (Results 101 - 125 of 125) sorted by relevance

12345

/vbox/src/recompiler/tcg/
H A Dtcg.h59 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
190 #define TCG_CALL_TYPE_REGPARM_1 0x0001 /* i386 style regparm call (1 reg) */
248 int reg; member in struct:TCGTemp
362 void tcg_set_frame(TCGContext *s, int reg,
365 TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name);
366 TCGv_i32 tcg_global_mem_new_i32(int reg, tcg_target_long offset,
380 TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name);
381 TCGv_i64 tcg_global_mem_new_i64(int reg, tcg_target_long offset,
/vbox/src/recompiler/tests/
H A Dtest-i386.c1362 printf("FS:reg = %04x:%08x\n", res2, res);
1584 static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg) argument
1586 return (uint8_t *)((seg << 4) + (reg & 0xffff));
2235 int i, reg;\
2239 asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
2243 reg);\
/vbox/src/VBox/Additions/x11/x11include/libdrm-2.4.13/
H A Di915_drm.h390 unsigned int reg:31; member in struct:drm_i915_mmio
H A Dradeon_drm.h270 unsigned char cmd_type, reg, n_bufs, flags; member in struct:__anon3644::__anon3652
/vbox/src/VBox/Devices/Graphics/shaderlib/
H A Dglsl_shader.c1440 static void shader_glsl_get_register_name(const struct wined3d_shader_register *reg, argument
1452 switch (reg->type)
1455 sprintf(register_name, "R%u", reg->idx);
1463 if (priv->cur_vs_args->swizzle_map & (1 << reg->idx)) *is_color = TRUE;
1464 sprintf(register_name, "attrib%u", reg->idx);
1471 DWORD idx = ((IWineD3DPixelShaderImpl *)This)->input_reg_map[reg->idx];
1474 if (reg->rel_addr)
1478 shader_glsl_add_src_param(ins, reg->rel_addr, WINED3DSP_WRITEMASK_0, &rel_param);
1519 if (reg->idx == 0) strcpy(register_name, "gl_Color");
1530 if (reg
3344 DWORD reg = ins->src[0].reg.idx; local
3483 DWORD reg = ins->dst[0].reg.idx; local
3497 DWORD reg = ins->dst[0].reg.idx; local
3511 DWORD reg = ins->dst[0].reg.idx; local
3535 DWORD reg = ins->dst[0].reg.idx; local
3560 DWORD reg = ins->dst[0].reg.idx; local
3577 DWORD reg = ins->dst[0].reg.idx; local
3609 DWORD reg = ins->dst[0].reg.idx; local
[all...]
H A Dwined3d_private.h621 struct wined3d_shader_register reg; member in struct:wined3d_shader_dst_param
629 struct wined3d_shader_register reg; member in struct:wined3d_shader_src_param
652 struct wined3d_shader_dst_param reg; member in struct:wined3d_shader_semantic
3186 static inline BOOL shader_is_scalar(const struct wined3d_shader_register *reg) argument
3188 switch (reg->type)
3192 if (reg->idx != 0) return TRUE;
3209 switch(reg->idx)
3220 switch(reg->immconst_type)
3233 static inline BOOL shader_constant_is_local(IWineD3DBaseShaderImpl* This, DWORD reg) { argument
3238 if(lconst->idx == reg) retur
[all...]
/vbox/src/VBox/Devices/Storage/
H A DDevFdc.cpp762 static uint32_t fdctrl_read (void *opaque, uint32_t reg) argument
767 switch (reg) {
793 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
798 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) argument
802 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
804 switch (reg) {
/vbox/src/VBox/Additions/WINNT/Graphics/Wine/wined3d/
H A Dglsl_shader.c1415 static void shader_glsl_get_register_name(const struct wined3d_shader_register *reg, argument
1427 switch (reg->type)
1430 sprintf(register_name, "R%u", reg->idx);
1438 if (priv->cur_vs_args->swizzle_map & (1 << reg->idx)) *is_color = TRUE;
1439 sprintf(register_name, "attrib%u", reg->idx);
1446 DWORD idx = ((IWineD3DPixelShaderImpl *)This)->input_reg_map[reg->idx];
1449 if (reg->rel_addr)
1453 shader_glsl_add_src_param(ins, reg->rel_addr, WINED3DSP_WRITEMASK_0, &rel_param);
1494 if (reg->idx == 0) strcpy(register_name, "gl_Color");
1505 if (reg
3221 DWORD reg = ins->src[0].reg.idx; local
3360 DWORD reg = ins->dst[0].reg.idx; local
3374 DWORD reg = ins->dst[0].reg.idx; local
3388 DWORD reg = ins->dst[0].reg.idx; local
3412 DWORD reg = ins->dst[0].reg.idx; local
3437 DWORD reg = ins->dst[0].reg.idx; local
3454 DWORD reg = ins->dst[0].reg.idx; local
3486 DWORD reg = ins->dst[0].reg.idx; local
[all...]
H A Darb_program_shader.c879 const struct wined3d_shader_register *reg, char *register_name, BOOL *is_color)
889 switch (reg->type)
892 sprintf(register_name, "R%u", reg->idx);
900 if (reg->idx == 0) strcpy(register_name, "fragment.color.primary");
905 if(reg->rel_addr)
908 shader_arb_get_src_param(ins, reg->rel_addr, 0, rel_reg);
912 DWORD idx = ctx->aL + reg->idx;
938 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg->idx);
950 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg->idx);
957 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg
878 shader_arb_get_register_name(const struct wined3d_shader_instruction *ins, const struct wined3d_shader_register *reg, char *register_name, BOOL *is_color) argument
1171 gen_color_correction(struct wined3d_shader_buffer *buffer, const char *reg, DWORD dst_mask, const char *one, const char *two, struct color_fixup_desc fixup) argument
1896 DWORD reg = dst->reg.idx; local
2024 DWORD reg = ins->dst[0].reg.idx; local
2044 DWORD reg = ins->dst[0].reg.idx; local
2065 DWORD reg = ins->dst[0].reg.idx; local
2090 DWORD reg = ins->dst[0].reg.idx; local
2113 DWORD reg = ins->dst[0].reg.idx; local
2155 DWORD reg = ins->dst[0].reg.idx; local
[all...]
H A Dwined3d_private.h610 struct wined3d_shader_register reg; member in struct:wined3d_shader_dst_param
618 struct wined3d_shader_register reg; member in struct:wined3d_shader_src_param
641 struct wined3d_shader_dst_param reg; member in struct:wined3d_shader_semantic
3151 static inline BOOL shader_is_scalar(const struct wined3d_shader_register *reg) argument
3153 switch (reg->type)
3157 if (reg->idx != 0) return TRUE;
3168 switch(reg->idx)
3179 switch(reg->immconst_type)
3192 static inline BOOL shader_constant_is_local(IWineD3DBaseShaderImpl* This, DWORD reg) { argument
3197 if(lconst->idx == reg) retur
[all...]
/vbox/src/recompiler/target-i386/
H A Dtranslate.c341 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) argument
349 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
350 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
351 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
354 tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
355 tcg_gen_or_tl(cpu_regs[reg
380 gen_op_mov_reg_T0(int ot, int reg) argument
385 gen_op_mov_reg_T1(int ot, int reg) argument
390 gen_op_mov_reg_A0(int size, int reg) argument
416 gen_op_mov_v_reg(int ot, TCGv t0, int reg) argument
434 gen_op_mov_TN_reg(int ot, int t_index, int reg) argument
439 gen_op_movl_A0_reg(int reg) argument
479 gen_op_add_reg_im(int size, int reg, int32_t val) argument
503 gen_op_add_reg_T0(int size, int reg) argument
532 gen_op_addl_A0_reg_sN(int shift, int reg) argument
544 gen_op_seg_check(int reg, bool keepA0) argument
598 gen_op_movl_A0_seg(int reg) argument
606 gen_op_addl_A0_seg(int reg) argument
619 gen_op_movq_A0_seg(int reg) argument
627 gen_op_addq_A0_seg(int reg) argument
636 gen_op_movq_A0_reg(int reg) argument
641 gen_op_addq_A0_reg_sN(int shift, int reg) argument
852 gen_extu(int ot, TCGv reg) argument
869 gen_exts(int ot, TCGv reg) argument
1003 gen_compute_eflags_c(TCGv reg) argument
1010 gen_compute_eflags(TCGv reg) argument
2408 gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) argument
3278 int modrm, mod, rm, reg, reg_addr, offset_addr; local
4421 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; local
[all...]
H A Dop_helper.c742 void helper_sync_seg(uint32_t reg) argument
744 if (env->segs[reg].newselector)
745 sync_seg(env, reg, env->segs[reg].newselector);
3616 target_ulong helper_read_crN(int reg) argument
3621 void helper_write_crN(int reg, target_ulong t0) argument
3625 void helper_movl_drN_T0(int reg, target_ulong t0) argument
3629 target_ulong helper_read_crN(int reg) argument
3633 helper_svm_check_intercept_param(SVM_EXIT_READ_CR0 + reg, 0);
3634 switch(reg) {
3653 helper_write_crN(int reg, target_ulong t0) argument
3682 helper_movl_drN_T0(int reg, target_ulong t0) argument
[all...]
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k.h888 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
1216 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) argument
1218 return readl(ah->ah_iobase + reg);
1224 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) argument
1226 writel(val, ah->ah_iobase + reg);
1233 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, argument
1240 data = ath5k_hw_reg_read(ah, reg);
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A Djme.h895 static inline uint32_t jread32(struct jme_adapter *jme, uint32_t reg) argument
897 return readl(jme->regs + reg);
900 static inline void jwrite32(struct jme_adapter *jme, uint32_t reg, uint32_t val) argument
902 writel(val, jme->regs + reg);
905 static void jwrite32f(struct jme_adapter *jme, uint32_t reg, uint32_t val) argument
910 writel(val, jme->regs + reg);
911 readl(jme->regs + reg);
H A Detherfabric.c374 efab_dword_t reg; local
376 reg.opaque = falcon_mdio_read ( efab, mmd,
378 status = EFAB_DWORD_FIELD ( reg,
1162 #define FCN_REVISION_REG(efab, reg) \
1163 ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
1165 #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \
1167 EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \
1169 EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
1175 unsigned int reg ) {
1222 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + local
1270 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + local
1330 efab_dword_t reg; local
1402 efab_oword_t reg; local
1424 efab_oword_t reg; local
1508 efab_oword_t reg; local
1531 efab_oword_t reg; local
1593 efab_oword_t reg; local
1646 efab_oword_t reg; local
1718 efab_oword_t reg; local
1904 efab_dword_t reg; local
1929 efab_dword_t reg; local
2125 efab_dword_t reg; local
2146 efab_dword_t reg; local
2168 efab_dword_t reg; local
2188 efab_dword_t reg; local
2213 efab_dword_t reg; local
2256 efab_dword_t reg; local
2663 int rc, reg; local
2743 int rc, reg, i; local
2843 efab_dword_t reg; local
3368 efab_oword_t reg; local
3408 efab_oword_t reg; local
3497 efab_oword_t reg; local
3601 efab_dword_t reg; local
3629 efab_dword_t reg; local
3793 efab_dword_t reg; local
[all...]
H A Dhfa384x.h2915 __hfa384x_getreg(hfa384x_t *hw, UINT reg);
2918 __hfa384x_setreg(hfa384x_t *hw, UINT16 val, UINT reg);
2921 __hfa384x_getreg_noswap(hfa384x_t *hw, UINT reg);
2924 __hfa384x_setreg_noswap(hfa384x_t *hw, UINT16 val, UINT reg);
2947 * reg Register identifier (offset for I/O based i/f)
2953 __hfa384x_getreg(hfa384x_t *hw, UINT reg) argument
2955 /* printk(KERN_DEBUG "Reading from 0x%0x\n", hw->membase + reg); */
2957 return wlan_inw_le16_to_cpu(hw->iobase+reg);
2959 return __le16_to_cpu(readw(hw->membase + reg));
2973 * reg Registe
2979 __hfa384x_setreg(hfa384x_t *hw, UINT16 val, UINT reg) argument
3005 __hfa384x_getreg_noswap(hfa384x_t *hw, UINT reg) argument
3030 __hfa384x_setreg_noswap(hfa384x_t *hw, UINT16 val, UINT reg) argument
[all...]
H A Dskge.h214 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
537 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
584 /* PHY addresses (bits 12..8 of PHY address reg) */
589 /* GPHY address (bits 15..11 of SMI control reg) */
2085 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2092 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2096 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2097 XM_SA = 0x0108, /* NA reg
2520 skge_read32(const struct skge_hw *hw, int reg) argument
2525 skge_read16(const struct skge_hw *hw, int reg) argument
2530 skge_read8(const struct skge_hw *hw, int reg) argument
2535 skge_write32(const struct skge_hw *hw, int reg, u32 val) argument
2540 skge_write16(const struct skge_hw *hw, int reg, u16 val) argument
2545 skge_write8(const struct skge_hw *hw, int reg, u8 val) argument
2555 xm_read32(const struct skge_hw *hw, int port, int reg) argument
2563 xm_read16(const struct skge_hw *hw, int port, int reg) argument
2579 xm_outhash(const struct skge_hw *hw, int port, int reg, const u8 *hash) argument
2588 xm_outaddr(const struct skge_hw *hw, int port, int reg, const u8 *addr) argument
2599 gma_read16(const struct skge_hw *hw, int port, int reg) argument
2604 gma_read32(const struct skge_hw *hw, int port, int reg) argument
2615 gma_set_addr(struct skge_hw *hw, int port, int reg, const u8 *addr) argument
[all...]
H A Dsky2.h245 #define RAM_BUFFER(port, reg) (reg | (port <<6))
327 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
575 #define SK_REG(port,reg) (((port)<<7)+(reg))
648 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
679 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
2096 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) argument
2101 sky2_read16(const struct sky2_hw *hw, unsigned reg) argument
2106 sky2_read8(const struct sky2_hw *hw, unsigned reg) argument
2111 sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) argument
2116 sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) argument
2121 sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) argument
2131 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) argument
2136 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) argument
2148 gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, const u8 *addr) argument
2157 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) argument
2162 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) argument
2167 sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) argument
2172 sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) argument
[all...]
/vbox/src/VBox/Additions/WINNT/Graphics/Wine_new/wined3d/
H A Darb_program_shader.c1007 const struct wined3d_shader_register *reg, char *register_name, BOOL *is_color)
1018 switch (reg->type)
1021 sprintf(register_name, "R%u", reg->idx[0].offset);
1029 if (!reg->idx[0].offset)
1036 if (reg->idx[0].rel_addr)
1039 shader_arb_get_src_param(ins, reg->idx[0].rel_addr, 0, rel_reg);
1043 DWORD idx = ctx->aL + reg->idx[0].offset;
1069 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg->idx[0].offset);
1081 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg->idx[0].offset);
1088 sprintf(register_name, "fragment.texcoord[%s + %u]", rel_reg, reg
1006 shader_arb_get_register_name(const struct wined3d_shader_instruction *ins, const struct wined3d_shader_register *reg, char *register_name, BOOL *is_color) argument
1291 gen_color_correction(struct wined3d_shader_buffer *buffer, const char *reg, DWORD dst_mask, const char *one, const char *two, struct color_fixup_desc fixup) argument
2023 DWORD reg = dst->reg.idx[0].offset; local
2144 DWORD reg = ins->dst[0].reg.idx[0].offset; local
2163 DWORD reg = ins->dst[0].reg.idx[0].offset; local
2183 DWORD reg = ins->dst[0].reg.idx[0].offset; local
2207 DWORD reg = ins->dst[0].reg.idx[0].offset; local
2229 DWORD reg = ins->dst[0].reg.idx[0].offset; local
2270 DWORD reg = ins->dst[0].reg.idx[0].offset; local
[all...]
H A Dglsl_shader.c1435 static void shader_glsl_get_register_name(const struct wined3d_shader_register *reg, argument
1449 if (reg->idx[0].offset != ~0U && reg->idx[0].rel_addr)
1450 shader_glsl_add_src_param(ins, reg->idx[0].rel_addr, WINED3DSP_WRITEMASK_0, &rel_param0);
1451 if (reg->idx[1].offset != ~0U && reg->idx[1].rel_addr)
1452 shader_glsl_add_src_param(ins, reg->idx[1].rel_addr, WINED3DSP_WRITEMASK_0, &rel_param1);
1455 switch (reg->type)
1458 sprintf(register_name, "R%u", reg->idx[0].offset);
1466 if (priv->cur_vs_args->swizzle_map & (1 << reg
3701 DWORD reg = ins->src[0].reg.idx[0].offset; local
3842 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3857 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3870 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3889 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3910 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3933 DWORD reg = ins->dst[0].reg.idx[0].offset; local
3963 DWORD reg = ins->dst[0].reg.idx[0].offset; local
[all...]
H A Dwined3d_private.h674 struct wined3d_shader_register reg; member in struct:wined3d_shader_dst_param
682 struct wined3d_shader_register reg; member in struct:wined3d_shader_src_param
692 struct wined3d_shader_dst_param reg; member in struct:wined3d_shader_semantic
2968 static inline BOOL shader_is_scalar(const struct wined3d_shader_register *reg) argument
2970 switch (reg->type)
2974 if (reg->idx[0].offset)
2987 switch (reg->idx[0].offset)
2998 return reg->immconst_type == WINED3D_IMMCONST_SCALAR;
3020 static inline BOOL shader_constant_is_local(const struct wined3d_shader *shader, DWORD reg) argument
3029 if (lconst->idx == reg)
[all...]
/vbox/src/VBox/Devices/Graphics/shaderlib/wine/include/wine/
H A Dmscvpdb.h1404 unsigned short reg; member in struct:codeview_symbol::__anon14121
1413 unsigned short reg; member in struct:codeview_symbol::__anon14122
1422 unsigned int type; /* check whether type & reg are correct */
1423 unsigned short reg; member in struct:codeview_symbol::__anon14123
1432 unsigned int type; /* check whether type & reg are correct */
1433 unsigned short reg; member in struct:codeview_symbol::__anon14124
/vbox/src/VBox/Devices/Graphics/vmsvga/
H A Dsvga3d_reg.h1658 uint32_t reg; /* register number */ member in struct:__anon14749
/vbox/src/VBox/Additions/WINNT/Graphics/Wine/include/wine/
H A Dmscvpdb.h1368 unsigned short reg; member in struct:codeview_symbol::__anon1465
1377 unsigned int type; /* check whether type & reg are correct */
1378 unsigned short reg; member in struct:codeview_symbol::__anon1466
1387 unsigned int type; /* check whether type & reg are correct */
1388 unsigned short reg; member in struct:codeview_symbol::__anon1467
/vbox/include/iprt/
H A Dx86.h2251 uint8_t reg[10]; member in struct:X86FPUMMX

Completed in 1504 milliseconds

12345