332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/**********************************************************
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Copyright 1998-2009 VMware, Inc. All rights reserved.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Permission is hereby granted, free of charge, to any person
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * obtaining a copy of this software and associated documentation
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * files (the "Software"), to deal in the Software without
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * restriction, including without limitation the rights to use, copy,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * modify, merge, publish, distribute, sublicense, and/or sell copies
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of the Software, and to permit persons to whom the Software is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * furnished to do so, subject to the following conditions:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The above copyright notice and this permission notice shall be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * included in all copies or substantial portions of the Software.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SOFTWARE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync **********************************************************/
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA 3D hardware definitions
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 3D Hardware Version
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * register. Is set by the host and read by the guest. This lets
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * us make new guest drivers which are backwards-compatible with old
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA hardware revisions. It does not let us support old guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * drivers. Good enough for now.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Generic Types
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef uint32_t SVGA3dBool; /* 32-bit Bool definition */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Surface formats.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If you modify this list, be sure to keep GLUtil.c in sync. It
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * includes the internal format definition of each surface in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * GLUtil_ConvertSurfaceFormat, and it contains a table of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * human-readable names in GLUtil_GetFormatName.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* signed formats */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* mixed formats */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Single- and dual-component floating point formats */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Any surface can be used as a buffer object, but SVGA3D_BUFFER is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the most efficient format to use when creating new surfaces
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * expressly for index or vertex data.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Packed Video formats */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Planar video formats */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Video format with alpha */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Advanced D3D9 depth formats. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These match the D3DFORMAT_OP definitions used by Direct3D. We need
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * them so that we can query the host for what the supported surface
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * operations are (when we're using the D3D backend, in particular),
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and so we can send those operations to the guest.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This format can be used as a render target if the current display mode
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is the same depth if the alpha channel is ignored. e.g. if the device
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * format op list entry for A8R8G8B8 should have this cap.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This format contains DirectDraw support (including Flip). This flag
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * should not to be set on alpha formats.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The rasterizer can support some level of Direct3D support in this format
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and implies that the driver can create a Context in this mode (for some
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * flag must also be set.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is set for a private format when the driver has put the bpp in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the structure.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format can be converted to any RGB format for which
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format can be used to create offscreen plain surfaces.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicated that this format can be read as an SRGB texture (meaning that the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * sampler will linearize the looked up data)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format can be used in the bumpmap instructions
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format can be sampled by the displacement map sampler
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format cannot be used with texture filtering
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that format conversions are supported to this RGB format if
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicated that this format can be written as an SRGB target (meaning that the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pixel pipe will DE-linearize data on output to format)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format cannot be used with alpha blending
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that the device can auto-generated sublevels for resources
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of this format
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format can be used by vertex texture sampler
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates that this format supports neither texture coordinate wrap
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * modes, nor mipmapping
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This structure is a conversion of SVGA3DFORMAT_OP_*.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Entries must be located at the same position.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef union {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * must fit in a uint32_t.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Output Gamma Level
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Output gamma effects the gamma curve of colors that are output from the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * rendering pipeline. A value of 1.0 specifies a linear color space. If the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * value is <= 0.0, gamma correction is ignored and linear color space is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_VERTEXMATERIAL_SPECULAR = 2 /* Use the value in the specular component */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The order and the values should not be changed
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the fog factor to be specified in the alpha component of the specular
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (a.k.a. secondary) vertex color.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * or per-pixel basis.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * computed using the eye Z value of each pixel (or vertex), whereas range-
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * based fog is computed using the actual distance (range) to the eye.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_3D_CMD_TEXTURESTATE Types. All value types
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * must fit in a uint32_t.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32_t */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32_t */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Sampler Gamma Level
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Sampler gamma effects the color of samples taken from the sampler. A
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * value of 1.0 will produce linear samples. If the value is <= 0.0 the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * gamma value is ignored and a linear space is used.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * disabled, and the rasterizer should use the magnification filter instead.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Texture argument constants for texture combiner
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* Modifiers for texture argument constants defined above. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is the limit to the number of fixed-function texture
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * transforms and texture coordinates we can support. It does *not*
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * correspond to the number of texture image units (samplers) we
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Vertex declarations
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * draw with any POSITIONT vertex arrays, the programmable vertex
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pipeline will be implicitly disabled. Drawing will take place as if
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * no vertex shader was bound.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED // Lookup a pre-sampled displacement map
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This structure is used for the divisor for geometry instancing;
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * it's a direct translation of the Direct3D equivalent.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef union {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * For index data, this number represents the number of instances to draw.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * For instance data, this number represents the number of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * instances/vertex in this stream
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is 1 if this is supposed to be the data that is repeated for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * every instance.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is 1 if this is supposed to be the per-instance data.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_QUERYSTATE_NEW = 3 /* Never submitted (For guest use only) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The maximum number of vertex arrays we're guaranteed to support in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_3D_CMD_DRAWPRIMITIVES.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The maximum number of primitive ranges we're guaranteed to support
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * in SVGA_3D_CMD_DRAWPRIMITIVES.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Identifiers for commands in the command FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the SVGA3D protocol and remain reserved; they should not be used in the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * IDs between 1040 and 1999 (inclusive) are available for use by the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * current SVGA3D protocol.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO clients other than SVGA3D should stay below 1000, or at 2000
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 // Deprecated
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 // Deprecated
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 // Deprecated
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Common substructures used in multiple FIFO commands:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef struct {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is a surface ID as well as face/mipmap indices.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A note on interpretation of pitch: This value of pitch is the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * number of bytes between vertically adjacent image
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blocks. Normally this is the number of bytes between the first
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pixel of two adjacent scanlines. With compressed textures,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * however, this may represent the number of bytes between
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * compression blocks rather than between rows of pixels.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * XXX: Compressed textures currently must be tightly packed in guest memory.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If the image is 1-dimensional, pitch is ignored.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If 'pitch' is zero, the SVGA3D device calculates a pitch value
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * assuming each row of blocks is tightly packed.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO command format definitions:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The data size header following cmdNum for every 3d command
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* uint32_t id; duplicate*/
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * optional mipmaps and cube faces.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * structures must have the same value of numMipLevels field.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * numMipLevels set to 0.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Followed by an SVGA3dSize structure for each mip level in each face.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A note on surface sizes: Sizes are always specified in pixels,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * even if the true surface size is not a multiple of the minimum
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * block size of the surface's format. For example, a 3x3x1 DXT1
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * compressed texture would actually be stored as a 4x4x1 image in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * structures must have the same value of numMipLevels field.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * numMipLevels set to 0.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Followed by an SVGA3dSize structure for each mip level in each face.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A note on surface sizes: Sizes are always specified in pixels,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * even if the true surface size is not a multiple of the minimum
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * block size of the surface's format. For example, a 3x3x1 DXT1
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * compressed texture would actually be stored as a 4x4x1 image in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of SVGA3dRect structures */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of SVGA3dCopyRect structures */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of SVGA3dRenderState structures */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of SVGA3dCopyBox structures */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If the discard flag is present in a surface DMA operation, the host may
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * discard the contents of the current mipmap level and face of the target
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * surface before applying the surface DMA contents.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If the unsynchronized flag is present, the host may perform this upload
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * without syncing to pending reads on this surface.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Guests *MUST* set the reserved bits to 0 before submitting the command
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * suffix as future flags may occupy these bits.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Followed by variable number of SVGA3dCopyBox structures. For consistency
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * in all clipping logic and coordinate translation, we define the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * "source" in each copyBox as the guest image and the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * "destination" as the host image, regardless of transfer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * direction.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * For efficiency, the SVGA3D device is free to copy more data than
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specified. For example, it may round copy boxes outwards such
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * that they lie on particular alignment boundaries.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3dCmdSurfaceDMASuffix --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a command suffix that will appear after a SurfaceDMA command in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the FIFO. It contains some extra information that hosts may use to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * optimize performance or protect the guest. This suffix exists to preserve
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * backwards compatibility while also allowing for new functionality to be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * implemented.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The maximum offset is used to determine the maximum offset from the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * guestPtr base address that will be accessed or written to during this
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * surfaceDMA. If the suffix is supported, the host will respect this
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * boundary while performing surface DMAs.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Defaults to MAX_uint32_t
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A set of flags that describes optimizations that the host may perform
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * while performing this surface DMA operation. The guest should never rely
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * on behaviour that is different when these flags are set for correctness.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Defaults to 0
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_3D_CMD_DRAW_PRIMITIVES --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command is the SVGA3D device's generic drawing entry point.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * It can draw multiple ranges of primitives, optionally using an
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * index buffer, using an arbitrary collection of vertex buffers.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Each SVGA3dVertexDecl defines a distinct vertex array to bind
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * during this draw call. The declarations specify which surface
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the vertex data lives in, what that vertex data is used for,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and how to interpret it.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Each SVGA3dPrimitiveRange defines a collection of primitives
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * to render using the same vertex arrays. An index buffer is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * optional.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A range hint is an optional specification for the range of indices
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * that the entire array will be used.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These are only hints. The SVGA3D device may use them for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * performance optimization if possible, but it's also allowed to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * ignore these values.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Define the origin and shape of a vertex or index array. Both
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 'offset' and 'stride' are in bytes. The provided surface will be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * reinterpreted as a flat array of bytes in the same format used
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * by surface DMA operations. To avoid unnecessary conversions, the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * surface should be created with the SVGA3D_BUFFER format.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Index 0 in the array starts 'offset' bytes into the surface.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Index 1 begins at byte 'offset + stride', etc. Array indices may
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * not be negative.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Describe a vertex array's data type, and define how it is to be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * used by the fixed function pipeline or the vertex shader. It
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * isn't useful to have two VertexDecls with the same
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * VertexArrayIdentity in one draw call.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Define a group of primitives to render, from sequential indices.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The value of 'primitiveType' and 'primitiveCount' imply the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * total number of vertices that will be rendered.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Optional index buffer. If indexArray.surfaceId is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * without an index buffer is identical to rendering with an index
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * buffer containing the sequence [0, 1, 2, 3, ...].
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If an index buffer is in use, indexWidth specifies the width in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * bytes of each index value. It must be less than or equal to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (Currently, the SVGA3D device requires index buffers to be tightly
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * packed. In other words, indexWidth == indexArray.stride)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Optional index bias. This number is added to all indices from
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * indexArray before they are used as vertex array indices. This
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can be used in multiple ways:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - When not using an indexArray, this bias can be used to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specify where in the vertex arrays to begin rendering.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - A positive number here is equivalent to increasing the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * offset in each vertex array.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - A negative number can be used to render using a small
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * vertex array and an index buffer that contains large
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * values. This may be used by some applications that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * crop a vertex buffer without modifying their index
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that rendering with a negative bias value may be slower and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * use more memory than rendering with a positive or zero bias.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * There are two variable size arrays after the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3dCmdDrawPrimitives structure. In order,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * they are:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_MAX_VERTEX_ARRAYS;
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the frequency divisor for the corresponding vertex decl).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of SVGA3dTextureState structures */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by variable number of DWORDs for shader bycode */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t cid; /* Same parameters passed to END_QUERY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t totalSize; /* Set by guest before query is ended. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync union { /* Set by host on exit from PENDING state */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a blit from an SVGA3D surface to a Screen Object. Just
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * like GMR-to-screen blits, this blit may be directed at a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specific screen or to the virtual coordinate space.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The blit copies from a rectangular region of an SVGA3D surface
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * image to a rectangular region of a screen or screens.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command takes an optional variable-length list of clipping
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * rectangles after the body of the command. If no rectangles are
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specified, there is no clipping region. The entire destRect is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * drawn to. If one or more rectangles are included, they describe
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * a clipping region. The clip rectangle coordinates are measured
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * relative to the top-left corner of destRect.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This clipping region serves multiple purposes:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - It can be used to perform an irregularly shaped blit more
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * efficiently than by issuing many separate blit commands.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - It is equivalent to allowing blits with non-integer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * source coordinates. You could blit just one half-pixel
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of a source, for example, by specifying a larger
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * destination rectangle than you need, then removing
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * part of it using a clip rectangle.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Limitations:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Currently, no backend supports blits from a mipmap or face
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * other than the first one.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGASignedRect destRect; /* Supports scaling if src/rest different size */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Clipping: zero or more SVGASignedRects follow */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Capability query index.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * fixed-function texture units available. Each of these units
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * work in both FFP and Shader modes, and they support texture
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * transforms and texture coordinates. The host may have additional
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * texture image units that are only usable with shaders.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * return TRUE. Even on physical hardware that does not support
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * these formats natively, the SVGA3D device will provide an emulation
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * which should be invisible to the guest OS.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * In general, the SVGA3D device should support any operation on
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * any surface format, it just may perform some of these
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * operations in software depending on the capabilities of the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * available physical hardware.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * XXX: In the future, we will add capabilities that describe in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * detail what formats are supported in hardware for what kinds
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of operations.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * render targets. This does no include the depth or stencil targets.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is the maximum number of SVGA context IDs that the guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is the maximum number of SVGA surface IDs that the guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Don't add new caps into the previous section; the values in this
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * enumeration must not change. You can put new values right before
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_DEVCAP_MAX.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA3D_DEVCAP_MAX /* This must be the last index. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef union {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#endif /* _SVGA3D_REG_H_ */