/*
* Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
* Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
*
* Modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
* Original from Linux kernel 2.6.30.
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATH5K_H
#define _ATH5K_H
#include <stddef.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/net80211.h>
#include <errno.h>
/* Keep all ath5k files under one errfile ID */
#define ARRAY_SIZE(a) (sizeof(a)/sizeof((a)[0]))
#include "desc.h"
#include "eeprom.h"
/* PCI IDs */
/****************************\
GENERIC DRIVER DEFINITIONS
\****************************/
/*
* AR5K REGISTER ACCESS
*/
/* First shift, then mask */
/* First mask, then shift */
/* Some registers can hold multiple values of interest. For this
* reason when we want to write to these registers we must first
* retrieve the values which we do not want to clear (lets call this
* old_data) and then set the register with this and our new_value:
* ( old_data | new_value) */
/* Access to PHY registers */
/* Access QCU registers per queue */
} while (0)
} while (0)
/* Used while writing initvals */
if (_i % 64) \
udelay(1); \
} while (0)
/* Register dumps are done per operation mode */
#define AR5K_INI_RFGAIN_5GHZ 0
/* TODO: Clean this up */
#define AR5K_INI_VAL_11A 0
#define AR5K_INI_VAL_XR 0
/* Used for BSSID etc manipulation */
)
/*
* Some tuneable values (these should be changeable by the user)
*/
#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
#define AR5K_TUNE_RADAR_ALERT 0
/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
* be the max value. */
/* This must be set when setting the RSSI threshold otherwise it can
* prevent a reset. If AR5K_RSSI_THR is read after writing to it
* the BMISS_THRES will be seen as 0, seems harware doesn't keep
* track of it. Max value depends on harware. For AR5210 this is just 7.
* For AR5211+ this seems to be up to 255. */
#define AR5K_TUNE_AIFS_XR 0
#define AR5K_TUNE_TPC_TXPOWER 0
#if __BYTE_ORDER == __BIG_ENDIAN
#define AR5K_INIT_CFG ( \
)
#else
#endif
/* Initial values */
#define AR5K_INIT_TRANSMIT_LATENCY ( \
(AR5K_INIT_USEC) \
)
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
)
#define AR5K_INIT_PROTO_TIME_CNTRL ( \
)
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
)
/* token to use for aifs, cwmin, cwmax in MadWiFi */
/* GENERIC CHIPSET DEFINITIONS */
/* MAC Chips */
enum ath5k_version {
AR5K_AR5210 = 0,
};
/* PHY Chips */
enum ath5k_radio {
AR5K_RF5110 = 0,
};
/*
*/
enum ath5k_srev_type {
};
struct ath5k_srev_name {
const char *sr_name;
unsigned sr_val;
};
/*
* Some of this information is based on Documentation from:
*
*
* Modulation for Atheros' eXtended Range - range enhancing extension that is
* supposed to double the distance an Atheros client device can keep a
* connection with an Atheros access point. This is achieved by increasing
* the receiver sensitivity up to, -105dBm, which is about 20dB above what
* the 802.11 specifications demand. In addition, new (proprietary) data rates
* are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
*
* Please note that can you either use XR or TURBO but you cannot use both,
* they are exclusive.
*
*/
/*
* Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
* signaling rate achieved through the bonding of two 54Mbit/s 802.11g
* channels. To use this feature your Access Point must also suport it.
* There is also a distinction between "static" and "dynamic" turbo modes:
*
* - Static: is the dumb version: devices set to this mode stick to it until
* the mode is turned off.
* - Dynamic: is the intelligent version, the network decides itself if it
* is ok to use turbo. As soon as traffic is detected on adjacent channels
* (which would get used in turbo mode), or when a non-turbo station joins
* the network, turbo mode won't be used until the situation changes again.
* Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
* monitors the used radio band in order to decide whether turbo mode may
* be used or not.
*
* This article claims Super G sticks to bonding of channels 5 and 6 for
* USA:
*
*
* The channel bonding seems to be driver specific though. In addition to
* deciding what channels will be used, these "Turbo" modes are accomplished
* by also enabling the following features:
*
* - Bursting: allows multiple frames to be sent at once, rather than pausing
* after each frame. Bursting is a standards-compliant feature that can be
* used with any Access Point.
* - Fast frames: increases the amount of information that can be sent per
* frame, also resulting in a reduction of transmission overhead. It is a
* proprietary feature that needs to be supported by the Access Point.
* - Compression: data frames are compressed in real time using a Lempel Ziv
* algorithm. This is done transparently. Once this feature is enabled,
* compression and decompression takes place inside the chipset, without
* putting additional load on the host CPU.
*
*/
enum ath5k_driver_mode {
AR5K_MODE_11A = 0,
};
enum {
};
/****************\
TX DEFINITIONS
\****************/
/*
* TX Status descriptor
*/
struct ath5k_tx_status {
} __attribute__ ((packed));
/**
* enum ath5k_tx_queue - Queue types used to classify tx queues.
* @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
* @AR5K_TX_QUEUE_DATA: A normal data queue
* @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
* @AR5K_TX_QUEUE_BEACON: The beacon queue
* @AR5K_TX_QUEUE_CAB: The after-beacon queue
* @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
*/
enum ath5k_tx_queue {
};
/*
* Queue syb-types to classify normal data queues.
* These are the 4 Access Categories as defined in
* WME spec. 0 is the lowest priority and 4 is the
* highest. Normal data that hasn't been classified
* goes to the Best Effort AC.
*/
enum ath5k_tx_queue_subtype {
};
/*
* Queue ID numbers as returned by the hw functions, each number
* represents a hw queue. If hw does not support hw queues
* (eg 5210) all data goes in one queue. These match
*/
enum ath5k_tx_queue_id {
};
/*
* Flags to set hw queue's parameters...
*/
/*
* A struct to hold tx queue's parameters
*/
struct ath5k_txq_info {
};
/*
* Transmit packet types.
* used on tx control descriptor
* TODO: Use them inside base.c corectly
*/
enum ath5k_pkt_type {
AR5K_PKT_TYPE_NORMAL = 0,
};
/*
* TX power and TPC settings
*/
)
)
/*
* DMA size definitions (2^n+2)
*/
enum ath5k_dmasize {
AR5K_DMASIZE_4B = 0,
};
/****************\
RX DEFINITIONS
\****************/
/*
* RX Status descriptor
*/
struct ath5k_rx_status {
};
/*
* TSF to TU conversion:
*
* TSF is a 64bit value in usec (microseconds).
* TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
* time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
*/
/*******************************\
GAIN OPTIMIZATION DEFINITIONS
\*******************************/
enum ath5k_rfgain {
AR5K_RFGAIN_INACTIVE = 0,
};
struct ath5k_gain {
};
/********************\
COMMON DEFINITIONS
\********************/
/* channel_flags */
/*
* Used internaly for reset_tx_queue).
* Also see struct struct net80211_channel.
*/
/*
* The following structure is used to map 2GHz channels to
* 5GHz Atheros channels.
* TODO: Clean up
*/
struct ath5k_athchan_2ghz {
};
/******************\
RATE DEFINITIONS
\******************/
/**
* Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
*
* The rate code is used to get the RX rate or set the TX rate on the
* hardware descriptors. It is also used for internal modulation control
* and settings.
*
* This is the hardware rate map we are aware of:
*
* rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
* rate_kbps 3000 1000 ? ? ? 2000 500 48000
*
* rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
* rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
*
* rate_code 17 18 19 20 21 22 23 24
* rate_kbps ? ? ? ? ? ? ? 11000
*
* rate_code 25 26 27 28 29 30 31 32
* rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
*
* "S" indicates CCK rates with short preamble.
*
* AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
* lowest 4 bits, so they are the same as below with a 0xF mask.
* (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
* We handle this in ath5k_setup_bands().
*/
/* B */
/* A and G */
/* XR */
/* adding this flag to rate_code enables short preamble */
/*
* Crypto definitions
*/
/***********************\
HW RELATED DEFINITIONS
\***********************/
/*
* Misc definitions
*/
return 0; \
} while (0)
/*
* Hardware interrupt abstraction
*/
/**
* enum ath5k_int - Hardware interrupt masks helpers
*
* @AR5K_INT_RX: mask to identify received frame interrupts, of type
* AR5K_ISR_RXOK or AR5K_ISR_RXERR
* @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
* @AR5K_INT_RXNOFRM: No frame received (?)
* @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
* Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
* LinkPtr is NULL. For more details, refer to:
* @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
* Note that Rx overrun is not always fatal, on some chips we can continue
* operation without reseting the card, that's why int_fatal is not
* common for all chips.
* @AR5K_INT_TX: mask to identify received frame interrupts, of type
* AR5K_ISR_TXOK or AR5K_ISR_TXERR
* @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
* @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
* We currently do increments on interrupt by
* (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
* @AR5K_INT_MIB: Indicates the Management Information Base counters should be
* checked. We should do this with ath5k_hw_update_mib_counters() but
* it seems we should also then do some noise immunity work.
* @AR5K_INT_RXPHY: RX PHY Error
* @AR5K_INT_RXKCM: RX Key cache miss
* @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
* beacon that must be handled in software. The alternative is if you
* have VEOL support, in that case you let the hardware deal with things.
* @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
* beacons from the AP have associated with, we should probably try to
* reassociate. When in IBSS mode this might mean we have not received
* any beacons from any local stations. Note that every station in an
* IBSS schedules to send beacons at the Target Beacon Transmission Time
* (TBTT) with a random backoff.
* @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
* @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
* until properly handled
* @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
* errors. These types of errors we can enable seem to be of type
* AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
* @AR5K_INT_GLOBAL: Used to clear and set the IER
* @AR5K_INT_NOCARD: signals the card has been removed
* @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
* bit value
*
* These are mapped to take advantage of some common bits
* between the MACs, to be able to set intr properties
* easier. Some of them are not used yet inside hw.c. Most map
* to the respective hw interrupt value as they are common amogst different
* MACs.
*/
enum ath5k_int {
};
/*
* Power management
*/
enum ath5k_power_mode {
AR5K_PM_UNDEFINED = 0,
};
/* GPIO-controlled software LED */
#define AR5K_SOFTLED_PIN 0
#define AR5K_SOFTLED_ON 0
/*
* Chipset capabilities -see ath5k_hw_get_capability-
* get_capability function is not yet fully implemented
* in ath5k so most of these don't work yet...
* TODO: Implement these & merge with _TUNE_ stuff above
*/
enum ath5k_capability_type {
};
/* XXX: we *may* move cap_range stuff to struct wiphy */
struct ath5k_capabilities {
/*
* Supported PHY modes
* (ie. CHANNEL_A, CHANNEL_B, ...)
*/
/*
* Frequency range (without regulation restrictions)
*/
struct {
} cap_range;
/*
* Values stored in the EEPROM (some of them...)
*/
/*
* Queue information
*/
struct {
} cap_queues;
};
/***************************************\
HARDWARE ABSTRACTION LAYER STRUCTURE
\***************************************/
/*
* Misc defines
*/
/* TODO: Clean up and merge with ath5k_softc */
struct ath5k_hw {
void *ah_iobase;
int ah_ier;
int ah_turbo;
int ah_calibration;
int ah_running;
int ah_single_chip;
int ah_combined_mic;
int ah_5ghz;
int ah_2ghz;
int ah_software_retry;
int ah_ant_diversity;
/* Current BSSID we are trying to assoc to / create.
* This is passed by mac80211 on config_interface() and cached here for
* use in resets */
int ah_gpio_npins;
struct {
/* Temporary tables used for interpolation */
int txp_tpc;
/* Values in 0.25dB units */
/* Values in dB units */
} ah_txpower;
/* noise floor from last periodic calibration */
/*
* Function pointers
*/
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
struct ath5k_tx_status *);
struct ath5k_rx_status *);
};
/*
* Prototypes
*/
extern int ath5k_bitrate_to_hw_rix(int bitrate);
/* LED functions */
/* Reset Functions */
extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel);
/* Power management functions */
extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration);
/* DMA Related Functions */
/* Interrupt handling */
/* EEPROM access functions */
/* Protocol Control Unit Functions */
/* BSSID Functions */
/* RX Filter functions */
/* ACK bit rate */
/* Key table (WEP) functions */
/* Queue Control Unit, DFS Control Unit Functions */
extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info);
enum ath5k_tx_queue queue_type,
struct ath5k_txq_info *queue_info);
/* Hardware Descriptor Functions */
/* GPIO Functions */
/* rfkill Functions */
/* Misc functions */
extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
/* Initial register settings functions */
/* Initialize RF */
struct net80211_channel *channel,
unsigned int mode);
/* PHY calibration */
/* Misc PHY functions */
/* TX power setup */
extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower);
/*
* Functions used internaly
*/
/*
* Translate usec to hw clock units
*/
{
}
/*
* Translate hw clock units to usec
*/
{
}
/*
* Read from a register
*/
{
}
/*
* Write to a register
*/
{
}
#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
/*
* Check if a register write has been completed
*/
{
int i;
for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
break;
break;
udelay(15);
}
return (i <= 0) ? -EAGAIN : 0;
}
/*
* Convert channel frequency to channel number
*/
{
if (freq == 2484)
return 14;
if (freq < 2484)
}
#endif
{
for (i = 0; i < bits; i++) {
}
return retval;
}
#endif