/illumos-gate/usr/src/uts/common/io/pciex/ |
H A D | pcie.c | 123 * pcie_serr_disable_flag : disable SERR only (in RCR and command reg) x86 1598 * Extract bdf from "reg" property. 1607 "reg", (int **)®spec, (uint_t *)®len) != DDI_SUCCESS) 1895 pci_regspec_t *reg; local 1918 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 1919 (caddr_t)®, &rlen) != DDI_PROP_SUCCESS) { 1921 "Can not read reg\n", ddi_driver_name(dip)); 1925 if (pcie_map_phys(ddi_get_child(current->dip), reg, &virt, 1947 pcie_unmap_phys(&config_handle, reg); 1949 kmem_free(reg, rle [all...] |
/illumos-gate/usr/src/uts/common/io/ral/ |
H A D | rt2560.c | 74 uint32_t reg; member in struct:__anon6466 81 uint8_t reg; member in struct:__anon6467 256 rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) argument 271 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val; 274 ral_debug(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val); 278 rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) argument 283 val = RT2560_BBP_BUSY | reg << 8; 298 rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) argument 314 (reg & 0x3); 318 sc->rf_regs[reg] [all...] |
/illumos-gate/usr/src/uts/common/io/rum/ |
H A D | rum.c | 71 uint32_t reg; member in struct:__anon6483 99 uint8_t reg; member in struct:__anon6484 306 rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len) argument 318 req.wIndex = reg; 339 rum_read(struct rum_softc *sc, uint16_t reg) argument 343 rum_read_multi(sc, reg, &val, sizeof (val)); 349 rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len) argument 361 req.wIndex = reg; 387 rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val) argument 391 rum_write_multi(sc, reg, 406 uint16_t reg = RT2573_MCU_CODE_BASE; local 922 rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val) argument 942 rum_bbp_read(struct rum_softc *sc, uint8_t reg) argument 971 rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val) argument [all...] |
/illumos-gate/usr/src/uts/common/io/rwd/ |
H A D | rt2661.c | 89 uint32_t reg; member in struct:__anon6486 96 uint8_t reg; member in struct:__anon6487 455 sc->bbp_prom[i].reg = val >> 8; 458 "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2139 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) argument 2155 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2193 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2199 if (sc->bbp_prom[i].reg == 0) 2201 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2209 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_ argument 2305 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) argument [all...] |
/illumos-gate/usr/src/uts/common/io/rwn/ |
H A D | rt2860.c | 89 uint32_t reg; member in struct:__anon6489 96 uint8_t reg; member in struct:__anon6490 417 sc->bbp[i].reg = val >> 8; 420 sc->bbp[i].reg, sc->bbp[i].val); 549 uint32_t reg; local 552 reg = (uint32_t)val << 16; 554 reg |= val; 556 sc->txpow20mhz[ridx] = reg; 557 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 558 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5gh 2020 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) argument 2056 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) argument 2112 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) argument [all...] |
/illumos-gate/usr/src/uts/common/io/sfe/ |
H A D | sfe.c | 427 int reg; local 447 reg = pci_config_get8(isa_handle, 0x48); 448 pci_config_put8(isa_handle, 0x48, reg | 0x40); 456 pci_config_put8(isa_handle, 0x48, reg); 1826 sfe_mii_read_sis900(struct gem_dev *dp, uint_t reg) argument 1833 cmd = MII_READ_CMD(dp->mii_phy_addr, reg); 1886 sfe_mii_write_sis900(struct gem_dev *dp, uint_t reg, uint16_t val) argument 1892 cmd = MII_WRITE_CMD(dp->mii_phy_addr, reg, val);
|
/illumos-gate/usr/src/uts/common/io/uath/ |
H A D | uath.c | 2408 uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data, argument 2414 write.reg = BE_32(reg); 2423 "could not write %d bytes to register 0x%02x\n", len, reg); 2429 uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val) argument 2434 write.reg = BE_32(reg); 2443 reg);
|
/illumos-gate/usr/src/uts/common/io/ural/ |
H A D | ural.c | 75 uint16_t reg; member in struct:__anon6553 101 uint8_t reg; member in struct:__anon6554 310 ural_read(struct ural_softc *sc, uint16_t reg) argument 323 req.wIndex = reg; 347 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) argument 359 req.wIndex = reg; 382 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) argument 393 req.wIndex = reg; 918 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) argument 933 tmp = reg << 938 ural_bbp_read(struct ural_softc *sc, uint8_t reg) argument 959 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) argument [all...] |
/illumos-gate/usr/src/uts/common/io/vr/ |
H A D | vr.h | 439 pci_regspec_t reg; member in struct:__anon6580
|
/illumos-gate/usr/src/uts/common/io/yge/ |
H A D | yge.c | 275 yge_mii_readreg(yge_port_t *port, uint8_t phy, uint8_t reg) argument 282 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 304 yge_mii_writereg(yge_port_t *port, uint8_t phy, uint8_t reg, uint16_t val) argument 311 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 323 yge_mii_read(void *arg, uint8_t phy, uint8_t reg) argument 329 rv = yge_mii_readreg(port, phy, reg); 335 yge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) argument 340 yge_mii_writereg(port, phy, reg, val); 2419 uint32_t reg; local 2486 reg [all...] |
/illumos-gate/usr/src/lib/libast/common/vmalloc/ |
H A D | vmhdr.h | 115 #define reg register macro
|
/illumos-gate/usr/src/uts/common/io/mii/ |
H A D | mii.c | 1063 phy_read(phy_handle_t *ph, uint8_t reg) argument 1067 return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg)); 1071 phy_write(phy_handle_t *ph, uint8_t reg, uint16_t val) argument 1075 (*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val);
|
/illumos-gate/usr/src/uts/common/io/mxfe/ |
H A D | mxfe.c | 1591 mxfe_miiread(mxfe_t *mxfep, int phy, int reg) argument 1595 return (mxfe_miiread98713(mxfep, phy, reg)); 1602 mxfe_miireadgeneral(mxfe_t *mxfep, int phy, int reg) argument 1627 mxfe_miiwritebit(mxfep, (reg & i) ? 1 : 0); 1644 mxfe_miiread98713(mxfe_t *mxfep, int phy, int reg) argument 1654 retval = mxfe_miireadgeneral(mxfep, phy, reg); 1660 mxfe_miiwrite(mxfe_t *mxfep, int phy, int reg, uint16_t val) argument 1664 mxfe_miiwrite98713(mxfep, phy, reg, val); 1672 mxfe_miiwritegeneral(mxfe_t *mxfep, int phy, int reg, uint16_t val) argument 1696 mxfe_miiwritebit(mxfep, (reg 1713 mxfe_miiwrite98713(mxfe_t *mxfep, int phy, int reg, uint16_t val) argument [all...] |
/illumos-gate/usr/src/uts/sun4u/serengeti/io/ |
H A D | sbdp_mem.c | 623 * To get it ready to OR it with the MC decode reg, 631 /* Convert tmp_base to be MC reg ready */ 647 * Step 2: Now rewrite the mc reg with present bit on. 662 mc_regspace reg; local 665 len = prom_getproplen(nodeid, "reg"); 669 if (prom_getprop(nodeid, "reg", (caddr_t)®) < 0) 674 *pa = ((uint64_t)reg.regspec_addr_hi) << 32; 675 *pa |= (uint64_t)reg.regspec_addr_lo; 749 SBDP_DBG_MEM("mc_get_idle_reg: failed to read reg pro 1510 mc_regspace reg; local 1577 mc_regspace reg; local [all...] |
/illumos-gate/usr/src/uts/sun4u/starcat/io/ |
H A D | schpc.c | 4061 int reg; member in struct:__anon9997 4094 int save_entry, list_entry, reg; local 4107 for (reg = 0; reg < 3; reg++) { 4108 if (ddi_regs_map_setup(schpc_p->schpc_slot[slot].devi, reg, 4110 saved_handle[reg]) != DDI_SUCCESS) { 4112 schpc_p->schpc_slot[slot].saved_regs_va[reg] = NULL; 4116 schpc_p->schpc_slot[slot].saved_regs_va[reg] = leaf_regs; 4126 while (save_reg_list[list_entry].reg ! 4159 int save_entry, list_entry, reg; local 4202 int reg, reads = 0; local 4295 int reg, writes = 0; local [all...] |
/illumos-gate/usr/src/uts/sun4u/sunfire/io/ |
H A D | sysctrl.c | 923 * Extract board # from reg property. 926 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&rp, &len) 928 DPRINTF(SYSC_DEBUG, ("devinfo node %s(%p) has no reg" 3272 uchar_t reg; member in struct:uart_cmd 3313 while (uart_table[i].reg != TABLE_END) { 3314 *(softsp->rcons_ctl) = uart_table[i].reg;
|
/illumos-gate/usr/src/uts/sun4v/io/ |
H A D | vnet.c | 416 uint64_t reg; local 461 reg = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 462 DDI_PROP_DONTPASS, "reg", -1); 463 if (reg == -1) { 466 vnetp->reg = reg; 503 status = vgen_init(vnetp, reg, vnetp->dip,
|
/illumos-gate/usr/src/uts/sun4v/sys/ |
H A D | vnet.h | 273 uint64_t reg; /* reg prop value */ member in struct:vnet
|
/illumos-gate/usr/src/uts/sun4u/io/ |
H A D | mc-us3.c | 151 static int mlayout_add(int mc_id, int bank_no, uint64_t reg, void *dimminfop); 903 "reg=0x%lx\n", softsp->memlayoutp, madreg)); 1577 mlayout_add(int mc_id, int bank_no, uint64_t reg, void *dimminfop) argument 1603 mcreg.madreg = reg; 1606 "%d, reg 0x%lx\n", mc_id, bank_no, reg));
|
/illumos-gate/usr/src/uts/sun4u/io/pci/ |
H A D | db21554.c | 940 pci_regspec_t *reg; local 983 * Step 2: program command reg on both primary and secondary 1010 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1013 "Failed to read reg property\n"); 1017 /* Find device node's base0 reg property and check its size */ 1020 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 1022 (reg[i].pci_size_low > DB_CSR_SIZE)) 1047 kmem_free(reg, length); 1737 /* get the reg numbe [all...] |
H A D | pcipsy.c | 327 cmn_err(CE_WARN, "%s%d: unable to map reg entry 0\n", 338 cmn_err(CE_WARN, "%s%d: unable to map reg entry 2\n", 353 cmn_err(CE_WARN, "%s%d: unable to map reg entry 1\n", 389 /* The psycho+ reg base is at 1fe.0000.0000 */ 396 /* The psycho+ config reg base is always the 2nd reg entry */ 412 ib_map_reg_get_cpu(volatile uint64_t reg) argument 414 return ((reg & COMMON_INTR_MAP_REG_TID) >> 512 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, "reg", 897 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg [all...] |
/illumos-gate/usr/src/uts/sun4u/io/px/ |
H A D | px_hlib.c | 48 * This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips 52 uint64_t reg; member in struct:px_pec_regs 2703 pec_config_state_regs[i].reg); 2777 CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i].reg, 2990 volatile uint64_t reg; local 2992 reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE); 2994 if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) { 2996 "tlu_pme_turn_off_generate = %x\n", reg); 3000 /* write to PME_Turn_off reg to boradcast */ 3001 reg | 3035 volatile uint64_t reg; local 3070 volatile uint64_t reg; local 3267 volatile uint64_t reg; local 3458 volatile uint64_t reg; local [all...] |
/illumos-gate/usr/src/uts/sun4u/opl/io/pcicmu/ |
H A D | pcicmu.c | 95 uint_t pcmu_intr_retry_intv = 5; /* for interrupt retry reg */ 713 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) { 1181 cmn_err(CE_WARN, "%s%d: unable to map reg entry 0\n", 1191 cmn_err(CE_WARN, "%s%d: unable to map reg entry 2\n", 1206 cmn_err(CE_WARN, "%s%d: unable to map reg entry 1\n", 1243 /* The CMU-CH config reg base is always the 2nd reg entry */ 1259 ib_map_reg_get_cpu(volatile uint64_t reg) argument 1261 return ((reg & PCMU_INTR_MAP_REG_TID) >> 1477 "pcmu_pbm_configure: conf status reg [all...] |
/illumos-gate/usr/src/uts/intel/io/drm/ |
H A D | radeon_state.c | 393 "Invalid indx_buffer reg address %08X\n", cmd[1]); 2824 int sz, reg; local 2832 reg = packet[id].start; 2845 OUT_RING(CP_PACKET0(reg, (sz - 1)));
|
/illumos-gate/usr/src/uts/i86xpv/io/psm/ |
H A D | xpv_psm.c | 1149 * Get device reg spec, first word has PCI bus and 1152 if (ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, "reg", 1159 * get PCI bus # from reg spec for device 1163 * get combined device/function from reg spec for device. 1208 * get PCI bus # and devfn from reg spec for device 1324 * get PCI bus # and devfn from reg spec for device 1512 ioapic_read(int apic_ix, uint32_t reg) argument 1517 apic.reg = reg; 1519 panic("read ioapic %d reg 1524 ioapic_write(int apic_ix, uint32_t reg, uint32_t value) argument [all...] |