25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * See the License for the specific language governing permissions
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and limitations under the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When distributing Covered Code, include this CDDL HEADER in each
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If applicable, add the following below this CDDL HEADER, with the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * fields enclosed by brackets "[]" replaced with your own identifying
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
193974072f41a843678abf5f61979c748687e66bSherry Moore * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL CMU-CH PCI nexus driver.
25cf1a301a396c38e8adf52c15f537b80d2483f7jluint32_t pcmu_spurintr_duration = 60000000; /* One minute */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The variable controls the default setting of the command register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for pci devices. See pcmu_init_child() for details.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This flags also controls the setting of bits in the bridge control
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * register pci to pci bridges. See pcmu_init_child() for details.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The following driver parameters are defined as variables to allow
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * patching for debugging and tuning. Flags that can be set on a per
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PBM basis are bit fields where the PBM device instance number maps
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to the bit position.
25cf1a301a396c38e8adf52c15f537b80d2483f7jluint_t pcmu_ecc_afsr_retries = 100; /* XXX - what's a good value? */
25cf1a301a396c38e8adf52c15f537b80d2483f7jluint_t pcmu_intr_retry_intv = 5; /* for interrupt retry reg */
25cf1a301a396c38e8adf52c15f537b80d2483f7jluint_t pcmu_panic_on_fatal_errors = 1; /* should be 1 at beta */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlhrtime_t pcmu_intrpend_timeout = 5ll * NANOSEC; /* 5 seconds in nanoseconds */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The following value is the number of consecutive unclaimed interrupts that
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * will be tolerated for a particular ino_p before the interrupt is deemed to
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * be jabbering and is blocked.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * function prototypes for dev ops routines:
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_open(dev_t *devp, int flags, int otyp, cred_t *credp);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_close(dev_t dev, int flags, int otyp, cred_t *credp);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_ctlops_poke(pcmu_t *pcmu_p, peekpoke_ctlops_t *in_args);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_ctlops_peek(pcmu_t *pcmu_p, peekpoke_ctlops_t *in_args,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl void *, void *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_intr_ops(dev_info_t *, dev_info_t *, ddi_intr_op_t,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void u2u_ittrans_init(pcmu_t *, u2u_ittrans_data_t **);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * bus ops and dev ops structures:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * module definitions:
193974072f41a843678abf5f61979c748687e66bSherry Moore "OPL CMU-CH PCI Nexus driver", /* Name of module. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * driver global data:
25cf1a301a396c38e8adf52c15f537b80d2483f7jlkmutex_t pcmu_global_mutex; /* attach/detach common struct lock */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlerrorq_t *pcmu_ecc_queue = NULL; /* per-system ecc handling queue */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize per-pci bus soft state pointer.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl e = ddi_soft_state_init(&per_pcmu_state, sizeof (pcmu_t), 1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (e != 0)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (e);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize global mutexes.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_init(&pcmu_global_mutex, NULL, MUTEX_DRIVER, NULL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Create the performance kstats.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Install the module.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (e != 0) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (e);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Remove the module.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (e != 0) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (e);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Destroy pcmu_ecc_queue, and set it to NULL.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Destroy the performance kstats.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Free the per-pci and per-CMU-CH soft state info and destroy
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * mutex for per-CMU-CH soft state.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (e);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* device driver entry points */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * attach entry point:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (cmd) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Allocate and get the per-pci soft state structure.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_init(&pcmu_p->pcmu_mutex, NULL, MUTEX_DRIVER, NULL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get key properties of the pci bridge node.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Map in the registers.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Due to unresolved hardware issues, disable PCIPM until
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the problem is fully understood.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_pwr_setup(pcmu_p, dip);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Make sure the CMU-CH control registers
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * are configured properly.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Make sure this instance has been suspended.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "instance NOT suspended\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG0(PCMU_DBG_ATTACH, dip, "unsupported attach op\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * detach entry point:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Make sure we are currently attached
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "failed - instance not attached\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (cmd) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Free the pci soft state structure and the rest of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * resources it's using.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Free the interrupt-priorities prop if we created it. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "interrupt-priorities");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG0(PCMU_DBG_DETACH, dip, "unsupported detach op\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED3 */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_open(dev_t *devp, int flags, int otyp, cred_t *credp)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the soft state structure for the device.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Handle the open by tracking the device state.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (pcmu_p->pcmu_soft_state == PCMU_SOFT_STATE_OPEN_EXCL) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG2(PCMU_DBG_IOCTL, dip, "dev=%x: cmd=%x\n", dev, cmd);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We can use the generic implementation for these ioctls
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (cmd) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * read devctl ioctl data
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (cmd) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG0(PCMU_DBG_IOCTL, dip, "DEVCTL_BUS_UNQUIESCE\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (rv);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int pcmu_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* bus driver entry points */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * bus map entry point:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * if map request is for an rnumber
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * get the corresponding regspec from device node
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * build a new regspec in our parent's format
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * build a new map_req with the new regspec
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * call up the tree to complete the mapping
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = get_pcmu_soft_state(ddi_get_instance(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG1(PCMU_DBG_MAP | PCMU_DBG_CONT, dip, " r#=%x", r_no);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_getlongprop(DDI_DEV_T_NONE, rdip, DDI_PROP_DONTPASS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* use "assigned-addresses" to relocate regspec within pci space */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* adjust regspec according to mapping request */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* use "ranges" to translate relocated pci regspec into parent space */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* DEBUG */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Set up protected environment. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Read the async fault register for the PBM to see it sees
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * a master-abort.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Take down protected environment. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_ctlops_poke(pcmu_t *pcmu_p, peekpoke_ctlops_t *in_args)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_ctlops_peek(pcmu_t *pcmu_p, peekpoke_ctlops_t *in_args, void *result)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * control ops entry point:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Requests handled completely:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_INITCHILD see pcmu_init_child() for details
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_UNINITCHILD
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_REPORTDEV see report_dev() for details
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_XLATE_INTRS nothing to do
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_REGSIZE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_NREGS
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_NINTRS
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_DVMAPAGESIZE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_POKE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_PEEK
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_QUIESCE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * DDI_CTLOPS_UNQUIESCE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * All others passed to parent.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = get_pcmu_soft_state(ddi_get_instance(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (op) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we are using the streaming cache, align at
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * least on a cache line boundary. Otherwise use
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * whatever alignment is passed in.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *((off_t *)result) = pcmu_get_reg_set_size(rdip, *((int *)arg));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (pcmu_ctlops_poke(pcmu_p, (peekpoke_ctlops_t *)arg));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (pcmu_ctlops_peek(pcmu_p, (peekpoke_ctlops_t *)arg,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Now pass the request up to our parent.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "passing request to parent: rdip=%s%d\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = get_pcmu_soft_state(ddi_get_instance(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* GetCap will always fail for all non PCI devices */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* PCI nexus driver supports only fixed interrupts */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH specifics implementation:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * interrupt mapping register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PBM configuration
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ECC and PBM error handling
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* called by pcmu_attach() DDI_ATTACH to initialize pci objects */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_rev = ddi_prop_get_int(DDI_DEV_T_ANY, pcmu_p->pcmu_dip,
c9b6d37c673213b7ad91d849a105790cb469f95bfherard * Due to a hardware bug, do not create kstat for DC systems
c9b6d37c673213b7ad91d849a105790cb469f95bfherard * with PCI hw revision less than 5.
c9b6d37c673213b7ad91d849a105790cb469f95bfherard PCICMU_OPL_DC_BINDING_NAME, strlen(PCICMU_OPL_DC_BINDING_NAME))
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_NOTE, "Interrupt register failure, returning 0x%x\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* called by pcmu_detach() DDI_DETACH to destroy pci objects */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* called by pcmu_attach() DDI_RESUME to (re)initialize pci objects */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* called by pcmu_detach() DDI_SUSPEND to suspend pci objects */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the interrupts property.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * figure out number of interrupts in the "interrupts" property
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and convert them all into ino.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl i = ddi_getprop(DDI_DEV_T_ANY, dip, 0, "#interrupt-cells", 1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < no_of_intrs; i++) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_intr_enable(pcmu_p, pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl intr_dist_add_weighted(pcmu_ib_intr_dist_all, pcmu_p->pcmu_ib_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (i);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_fix_ranges - fixes the config space entry of the "ranges"
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * property on CMU-CH platforms
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((rng_p->child_high & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * map_pcmu_registers
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This function is called from the attach routine to map the registers
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * accessed by this driver.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * used by: pcmu_attach()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * return value: DDI_FAILURE on failure
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_regs_map_setup(dip, 0, &pcmu_p->pcmu_address[0], 0, 0,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We still use pcmu_address[2]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_regs_map_setup(dip, 2, &pcmu_p->pcmu_address[2], 0, 0,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The second register set contains the bridge's configuration
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * header. This header is at the very beginning of the bridge's
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * configuration space. This space has litte-endian byte order.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_regs_map_setup(dip, 1, &pcmu_p->pcmu_address[1], 0,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCI_CONF_HDR_SIZE, &attr, &pcmu_p->pcmu_ac[1]) != DDI_SUCCESS) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * unmap_pcmu_registers:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This routine unmap the registers mapped by map_pcmu_registers.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * used by: pcmu_detach()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * return value: none
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * These convenience wrappers relies on map_pcmu_registers() to setup
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_address[0-2] correctly at first.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* The CMU-CH config reg base is always the 2nd reg entry */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return ((mondo) | (cpu_id << PCMU_INTR_MAP_REG_TID_SHIFT) |
25cf1a301a396c38e8adf52c15f537b80d2483f7jlib_clear_intr_reg_addr(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pib_p->pib_obio_intr_map_regs = a + PCMU_IB_OBIO_INTR_MAP_REG_OFFSET;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (a);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Return the cpuid to to be used for an ino.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * On multi-function pci devices, functions have separate devinfo nodes and
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * interrupts.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This function determines if there is already an established slot-oriented
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * interrupt-to-cpu binding established, if there is then it returns that
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * cpu. Otherwise a new cpu is selected by intr_dist_cpuid().
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The devinfo node we are trying to associate a cpu with is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ino_p->pino_ih_head->ih_dip.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_intr_dist_cpuid(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* must be CMU-CH driver parent (not ebus) */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * From PCI 1275 binding: 2.2.1.3 Unit Address representation:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Since the "unit-number" is the address that appears in on Open
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Firmware 'device path', it follows that only the DD and DD,FF
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * forms of the text representation can appear in a 'device path'.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The rdip unit address is of the form "DD[,FF]". Define two
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * unit address strings that represent same-slot use: "DD" and "DD,".
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The first compare uses strcmp, the second uses strncmp.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Search the established ino list for devinfo nodes bound
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to an ino that matches one of the slot use strings.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (sino_p = pib_p->pib_ino_lst; sino_p; sino_p = sino_p->pino_next) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* skip self and non-established */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((sino_p == ino_p) || (sino_p->pino_established == 0))
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* skip non-siblings */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* must be CMU-CH driver parent (not ebus) */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "pcicmu`pcmu_intr_dist_cpuid "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "%s#%d %s: cpu %d established "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* If a slot use match is found then use established cpu */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cpu_id = sino_p->pino_cpuid; /* target established cpu */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl u2u_ittrans_uninit((u2u_ittrans_data_t *)pcb_p->pcb_ittrans_cookie);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_ecc_add_intr(pcmu_t *pcmu_p, int inum, pcmu_ecc_intr_info_t *eii_p)
b0fc0e77220f1fa4c933fd58a4e1dedcd650b0f1govinda VERIFY(add_ivintr(mondo, pcmu_pil[inum], (intrfunc)pcmu_ecc_intr,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_ecc_rem_intr(pcmu_t *pcmu_p, int inum, pcmu_ecc_intr_info_t *eii_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define pbm_err ((PCMU_PCI_AFSR_E_MASK << PCMU_PCI_AFSR_PE_SHIFT) | \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Clear any PBM errors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Clear error bits in configuration status register.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "pcmu_pbm_configure: conf status reg==%x\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer",
c9b6d37c673213b7ad91d849a105790cb469f95bfherard (int)pcbm_p->pcbm_config_header->ch_latency_timer_reg);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Disable error and streaming byte hole interrupts via the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PBM control register.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Disable error interrupts via the interrupt mapping register.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pa = (uint64_t)hat_getpfnum(kas.a_hat, pcmu_p->pcmu_address[0]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcb_p->pcb_base_pa = pa = pa >> (32 - MMU_PAGESHIFT) << 32;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcb_p->pcb_map_pa = pa + PCMU_IB_OBIO_INTR_MAP_REG_OFFSET;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcb_p->pcb_clr_pa = pa + PCMU_IB_OBIO_CLEAR_INTR_REG_OFFSET;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcb_p->pcb_obsta_pa = pa + PCMU_IB_OBIO_INTR_STATE_DIAG_REG;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Clear any pending address parity errors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pecc_p->pecc_ue.pecc_offset_mask = PCMU_ECC_UE_AFSR_DW_OFFSET;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pecc_p->pecc_ue.pecc_offset_shift = PCMU_ECC_UE_AFSR_DW_OFFSET_SHIFT;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the base virtual address for the PBM control block.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the virtual address of the PCI configuration header.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This should be mapped little-endian.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the virtual addresses for control, error and diag
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * registers.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_ctrl_reg = (uint64_t *)(a + PCMU_PCI_CTRL_REG_OFFSET);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_diag_reg = (uint64_t *)(a + PCMU_PCI_DIAG_REG_OFFSET);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH Performance Events.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Create the picN kstat's.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_name_kstat = (pcmu_ksinfo_t *)kmem_alloc(sizeof (pcmu_ksinfo_t),
c9b6d37c673213b7ad91d849a105790cb469f95bfherard sizeof (pcicmu_pcmu_events) / sizeof (pcmu_kev_mask_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Called from _fini()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Create the performance 'counters' kstat.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t regbase = va_to_pa((void *)get_reg_base(pcmu_p));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_uksp = pcmu_create_cntr_kstat(pcmu_p, "pcmup",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * u2u_ittrans_init() is caled from in pci.c's pcmu_cb_setup() per CMU.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Second argument "ittrans_cookie" is address of pcb_ittrans_cookie in
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcb_p member. allocated interrupt block is returned in it.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlu2u_ittrans_init(pcmu_t *pcmu_p, u2u_ittrans_data_t **ittrans_cookie)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Allocate the data structure to support U2U's
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * interrupt target translations.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get other properties, "board#"
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* this cannot happen on production systems */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_PANIC, "u2u:Invalid property;board = %d", board);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize interrupt target translations mutex.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_init(&(u2u_trans_p->u2u_ittrans_lock), "u2u_ittrans_lock",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get U2U's registers space by ddi_regs_map_setup(9F)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl REGS_INDEX_OF_U2U, (caddr_t *)(&(u2u_trans_p->u2u_regs_base)),
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * check result of ddi_regs_map_setup().
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_PANIC, "u2u%d: registers map setup failed", board);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Read Port-id(1 byte) in u2u
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * u2u_ittras_resume() is called from pcmu_obj_resume() at DDI_RESUME entry.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Set U2U Data Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* This index was not set */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * u2u_ittras_uninit() is called from ib_destroy() at detach,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * or occuring error in attach.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return; /* not support */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return; /* illeagal case */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kmem_free((void *)ittrans_cookie, sizeof (u2u_ittrans_data_t));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This routine,u2u_translate_tgtid(, , cpu_id, pino_map_reg),
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * searches index having same value of pino_map_reg, or empty.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Then, stores cpu_id in a U2U Data Register as this index,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and return this index.
c9b6d37c673213b7ad91d849a105790cb469f95bfherard (u2u_ittrans_data_t *)(pcmu_p->pcmu_cb_p->pcb_ittrans_cookie);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Decide index No. of U2U Data registers in either
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * already used by same pino_map_reg, or empty.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* already used this pino_map_reg */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * set cpu_id into u2u_data_reg by index.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ((uint64_t)(u2u_regs_base
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * + U2U_DATA_REGISTER_OFFSET))[index] = cpu_id;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Set cpu_id into U2U Data register[index]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *(volatile uint32_t *) (data_reg_addr) = (uint32_t)cpu_id;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Setup for software, excepting at panicing.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and rebooting, etc...?
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * u2u_ittrans_cleanup() is called from common_pcmu_ib_intr_disable()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * after called intr_rem_cpu(mondo).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return; /* illeagal case */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_ecc_classify, called by ecc_handler to classify ecc errors
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and determine if we should panic or not.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_ecc_classify(uint64_t err, pcmu_ecc_errstate_t *ecc_err_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* LINTED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = ecc_err_p->ecc_ii_p.pecc_p->pecc_pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Get the parent bus id that caused the error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ecc_err_p->ecc_dev_id = (ecc_err_p->ecc_afsr & PCMU_ECC_UE_AFSR_ID)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Determine the doubleword offset of the error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_ECC_UE_AFSR_DW_OFFSET) >> PCMU_ECC_UE_AFSR_DW_OFFSET_SHIFT;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Determine the primary error type.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl switch (err) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* For CMU-CH, a UE is always fatal. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_pbm_classify, called by pcmu_pbm_afsr_report to classify piow afsr.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Function used to clear PBM/PCI/IOMMU error state after error handling
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is complete. Only clearing error bits which have been logged. Called by
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_pbm_err_handler and pcmu_bus_exit.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_clear_error(pcmu_t *pcmu_p, pcmu_pbm_errstate_t *pbm_err_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ASSERT(MUTEX_HELD(&pcbm_p->pcbm_pcmu_p->pcmu_err_mutex));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *pcbm_p->pcbm_async_flt_status_reg = pbm_err_p->pbm_afsr;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * For ddi_peek treat all events as nonfatal. We only
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * really call this function so that pcmu_clear_error()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and ndi_fm_handler_dispatch() will get called.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * For ddi_poke we can treat as nonfatal if the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * following conditions are met :
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 1. Make sure only primary error is MA/TA
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 2. Make sure no secondary error
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 3. check pci config header stat reg to see MA/TA is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * logged. We cannot verify only MA/TA is recorded
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * since it gets much more complicated when a
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PCI-to-PCI bridge is present.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ret = pcmu_pbm_afsr_report(dip, derr->fme_ena, &pbm_err);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ret = pcmu_cfg_report(dip, derr, &pbm_err.pcbm_pci, caller, prierr);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Cleanup and reset error bits */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL :
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_cfg_stat = pcbm_p->pcbm_config_header->ch_status_reg;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((pcmu_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB |
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Function used to gather PBM/PCI error state for the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_pbm_err_handler. This function must be called while pcmu_err_mutex
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is held.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_errstate_get(pcmu_t *pcmu_p, pcmu_pbm_errstate_t *pbm_err_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Capture all pbm error state for later logging
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pbm_err_p->pbm_afsr = *pcbm_p->pcbm_async_flt_status_reg;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pbm_err_p->pcbm_pci.pcmu_pa = *pcbm_p->pcbm_async_flt_addr_reg;
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for poke() support - called from POKE_FLUSH. Spin waiting
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for MA, TA or SERR to be cleared by a pcmu_pbm_error_intr().
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We have to wait for SERR too in case the device is beyond
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * a pci-pci bridge.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PCI detected ECC errorq, to schedule async handling
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * of ECC errors and logging.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The errorq is created here but destroyed when _fini is called
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for the pci module.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize error handling mutex.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Function used to post PCI block module specific ereports.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_WARN, "%s %s: %s %s=0x%lx, %s=0x%lx, %s=0x%lx %s=0x%x",