Lines Matching defs:reg
48 * This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips
52 uint64_t reg;
2703 pec_config_state_regs[i].reg);
2777 CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i].reg,
2990 volatile uint64_t reg;
2992 reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE);
2994 if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) {
2996 "tlu_pme_turn_off_generate = %x\n", reg);
3000 /* write to PME_Turn_off reg to boradcast */
3001 reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO);
3002 CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg);
3035 volatile uint64_t reg;
3037 reg = CSR_XR(csr_base, TLU_CONTROL);
3038 if (!(reg & (1ull << TLU_REMAIN_DETECT_QUIET))) {
3050 reg = CSR_XR(csr_base, TLU_CONTROL);
3051 reg &= ~(1ull << TLU_REMAIN_DETECT_QUIET);
3052 CSR_XS(csr_base, TLU_CONTROL, reg);
3070 volatile uint64_t reg;
3077 reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE);
3078 if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) {
3091 reg = CSR_XR(csr_base, TLU_SLOT_STATUS);
3092 if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) ||
3093 (reg & (1ull << TLU_SLOT_STATUS_MRLS))) {
3095 reg);
3162 reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS);
3164 if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
3167 (reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) &&
3168 ((reg &
3195 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
3197 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P;
3199 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P;
3201 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S;
3203 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S;
3204 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
3210 reg = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES);
3211 reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK <<
3213 reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
3215 reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV);
3216 CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
3219 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3220 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3221 reg = pcie_slotctl_pwr_indicator_set(reg,
3223 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3250 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3251 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3252 reg = pcie_slotctl_pwr_indicator_set(reg,
3254 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3267 volatile uint64_t reg;
3284 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
3285 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
3289 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
3324 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3325 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3326 reg = pcie_slotctl_pwr_indicator_set(reg,
3328 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3331 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3332 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
3333 reg = pcie_slotctl_attn_indicator_set(reg,
3335 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3359 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3360 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
3361 reg = pcie_slotctl_attn_indicator_set(reg,
3363 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3458 volatile uint64_t reg;
3474 reg = CSR_XR((caddr_t)pxu_p->px_address[PX_REG_CSR],
3476 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
3481 TLU_OTHER_EVENT_LOG_ENABLE, reg);