Searched defs:reg (Results 151 - 175 of 341) sorted by relevance

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/illumos-gate/usr/src/uts/i86pc/io/
H A Dimmu_dmar.c644 struct regspec reg; local
652 reg.regspec_bustype = 0;
653 reg.regspec_addr = drhd->dr_regs;
654 reg.regspec_size = IMMU_REGSZ;
657 * update the reg properties
659 * reg property will be used for register
670 dip, "reg", (int *)&reg,
H A Dimmu_regs.c824 immu_regs_get64(immu_t *immu, uint_t reg) argument
826 return (get_reg64(immu, reg));
830 immu_regs_get32(immu_t *immu, uint_t reg) argument
832 return (get_reg32(immu, reg));
836 immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val) argument
838 put_reg64(immu, reg, val);
842 immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val) argument
844 put_reg32(immu, reg, val);
/illumos-gate/usr/src/uts/i86pc/io/pci/
H A Dpci.c335 struct regspec reg; local
372 * get ALL "reg" properties for dip, select the one of
374 * is identical to the "reg" property, so there is no
381 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp,
433 reg.regspec_bustype = 1;
445 reg.regspec_bustype = 0;
451 reg.regspec_addr = pci_rp->pci_phys_low;
452 reg.regspec_size = pci_rp->pci_size_low;
454 mp->map_obj.rp = ®
509 reg
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/illumos-gate/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c424 struct regspec reg; local
446 * get ALL "reg" properties for dip, select the one of
448 * is identical to the "reg" property, so there is no
455 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp,
495 reg.regspec_bustype = 1;
528 reg.regspec_bustype = 0;
543 reg.regspec_addr = pci_rp->pci_phys_low;
544 reg.regspec_size = pci_rp->pci_size_low;
546 mp->map_obj.rp = ®
649 reg
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/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dunm_nic_ctx.c260 u32 cap, reg; local
351 reg = LE_TO_HOST_32(prsp_rds[i].host_producer_crb);
352 rcv_desc->host_rx_producer = UNM_NIC_REG(reg - 0x200);
357 reg = LE_TO_HOST_32(prsp_sds[0].host_consumer_crb);
358 recv_ctx->host_sds_consumer = UNM_NIC_REG(reg - 0x200);
360 reg = LE_TO_HOST_32(prsp_sds[0].interrupt_crb);
361 adapter->interrupt_crb = UNM_NIC_REG(reg - 0x200);
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hw.c940 uint8_t *reg; local
946 reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0];
948 "reg = 0x%016llX index = 0x%08X value = 0x%08X",
949 reg, buf[0], buf[1]));
950 NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]);
1169 uint16_t reg; local
1173 reg = *(uint16_t *)mp->b_rptr;
1174 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg,
1176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X",
1177 reg, *(uint16_
1186 uint8_t reg; local
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/illumos-gate/usr/src/uts/common/io/pciex/hotplug/
H A Dpciehpc.c143 /* HPC access is non-standard; use the supplied reg ops */
726 uint16_t reg; local
729 reg = pciehpc_reg_get16(ctrl_p,
733 reg &= ~(PCIE_SLOTCTL_INTR_MASK);
735 PCIE_SLOTCTL, reg);
738 reg = pciehpc_reg_get16(ctrl_p,
741 bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
876 uint16_t reg; local
879 reg = pciehpc_reg_get16(ctrl_p,
882 bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
911 uint16_t reg; local
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H A Dpcishpc.c100 static uint32_t pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg);
101 static void pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg,
172 PCIE_DBG("SHPC Cfg reg 0x%02x: %08x\n", i,
261 uint32_t irq_locator, irq_serr_locator, reg; local
280 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
282 if (reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) {
289 if (reg & PCI_HP_SERR_INT_ARBITER_IRQ) {
296 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
309 reg = pcishpc_read_reg(ctrl_p,
312 if (reg
1114 uint32_t reg; local
1160 uint32_t reg; local
1254 uint32_t reg; local
1355 uint32_t reg; local
1790 uint32_t reg; local
1835 uint32_t reg, cmd_code; local
2357 pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg) argument
2385 pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg, uint32_t data) argument
2424 uint32_t reg; local
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/illumos-gate/usr/src/uts/common/io/ral/
H A Drt2560_var.h179 uint8_t reg; member in struct:rt2560_softc::__anon6469
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-mgmt.c502 int reg = (queue / 4); local
505 addr = (reg == 1)? (&bar0->ring_bump_counter2) :
/illumos-gate/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; local
156 reg = phy_read(ph, MVPHY_PSC);
158 reg |= MV_PSC_AUTO_MDIX;
159 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
160 reg |= MV_PSC_LPNP;
165 phy_write(ph, MVPHY_PSC, reg);
184 uint16_t reg; local
193 reg = phy_read(ph, MII_CONTROL);
194 reg |= MII_CONTROL_RESET;
195 phy_write(ph, MII_CONTROL, reg);
210 uint16_t reg; local
227 uint16_t reg; local
289 uint16_t reg; local
324 uint16_t reg; local
340 uint16_t reg; local
362 uint16_t reg, page; local
397 uint16_t reg; local
420 uint16_t reg; local
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/illumos-gate/usr/src/uts/sun4u/starcat/io/
H A Dsc_gptwocfg.c844 gptwo_regspec_t *reg; local
893 DDI_PROP_DONTPASS, "reg", (caddr_t)&reg, &size)
897 * This AXQ node does not have a reg property.
900 "have a 'reg' property\n", (void *)dip));
905 id = ((reg[0].gptwo_phys_hi & 1) << 9) |
906 ((reg[0].gptwo_phys_low & 0xff800000) >> 23);
908 kmem_free(reg, size);
949 gptwo_regspec_t reg[2]; local
984 reg[
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/illumos-gate/usr/src/uts/sun4u/sys/
H A Dsbbcvar.h59 * definition of sbbc child reg spec entry:
100 pci_regspec_t *reg; member in struct:sbbcsoft
/illumos-gate/usr/src/uts/sun4v/io/
H A Dvnet_dds.c66 /* For "reg" property */
707 DDI_PROP_DONTPASS, "reg", (int **)&reg_p, &reglen);
709 DWARN(NULL, "Failed to get reg property dip=0x%p", dip);
747 DDI_PROP_DONTPASS, "reg", (int **)&reg_p, &reglen);
749 DWARN(NULL, "Failed to get reg property dip=0x%p", dip);
776 vdds_reg_t reg; local
806 * create "reg" property. The first 28 bits of
810 reg.addr_hi = 0xc0000000 | NIUCFGHDL(cba->cookie);
811 reg.addr_lo = 0;
812 reg
878 vdds_reg_t reg; local
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/illumos-gate/usr/src/uts/sun4/sys/
H A Debus.h79 * definition of ebus reg spec entry:
122 pci_regspec_t *reg; member in struct:__anon9761
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus.c766 uint64_t reg; local
772 reg = get_safari_config();
773 reg &= ~SAFARI_CONFIG_ECLK_MASK;
774 reg |= bceclk->mask;
775 set_safari_config(reg);
/illumos-gate/usr/src/uts/sun4u/io/i2c/nexus/
H A Dsmbus.c71 static void smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags);
72 static uint8_t smbus_get(smbus_t *smbus, uint8_t reg);
515 "reg", (caddr_t)regs, &len);
518 cmn_err(CE_WARN, "cannot get reg property");
527 * The reg property contains an unused first element (which is
734 smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags) argument
741 ddi_put8(hp, &reg_addr[reg], data);
744 &reg_addr[reg], data));
756 smbus_get(smbus_t *smbus, uint8_t reg) argument
763 data = ddi_get8(hp, &regaddr[reg]);
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/illumos-gate/usr/src/uts/sun4u/montecarlo/sys/
H A Dacebus.h84 pci_regspec_t *reg; member in struct:__anon9842
103 * definition of ebus reg spec entry:
/illumos-gate/usr/src/uts/intel/io/pci/
H A Dpci_pci.c556 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg",
607 /* get child "reg" property */
609 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
843 uint16_t reg; local
849 reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF);
852 reg |= PCI_HTCAP_MSIMAP_ENABLE;
856 reg &= ~(uint16_t)PCI_HTCAP_MSIMAP_ENABLE;
859 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg);
/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c464 x86_error_reg_t *reg; local
491 reg = tbl->error_regs;
492 for (j = 0; j < tbl->error_regs_len; j++, reg++) {
495 switch (reg->size) {
498 reg->offset);
500 ((data & reg->mask) | reg->value2) :
501 ((data & reg->mask) | reg->value1));
502 pci_config_put32(cfg_hdl, reg
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/illumos-gate/usr/src/uts/i86pc/os/cpupm/
H A Dcpu_acpi.c748 AML_RESOURCE_GENERIC_REGISTER *reg; local
752 reg = (AML_RESOURCE_GENERIC_REGISTER *)
754 cstate->cs_addrspace_id = reg->AddressSpaceId;
755 cstate->cs_address = reg->Address;
/illumos-gate/usr/src/uts/common/io/efe/
H A Defe.c498 efe_mii_read(void *arg, uint8_t phy, uint8_t reg) argument
503 reg << MMCTL_PHYREG | phy << MMCTL_PHYADDR);
517 efe_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t data) argument
524 reg << MMCTL_PHYREG | phy << MMCTL_PHYADDR);
/illumos-gate/usr/src/uts/common/os/
H A Dbrand.c471 brand_proc_reg_t reg; local
506 if (copyin((void *)arg1, &reg, sizeof (reg)) != 0)
515 reg.sbr_version = reg32.sbr_version;
516 reg.sbr_handler = (caddr_t)(uintptr_t)reg32.sbr_handler;
520 if (reg.sbr_version != brandvers)
522 spd->spd_handler = reg.sbr_handler;
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82598.c413 u32 reg; local
538 reg = hw->fc.pause_time * 0x00010001;
540 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
1070 * @reg: analog register to read
1075 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) argument
1082 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1094 * @reg: atlas register to write
1099 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) argument
1105 atlas_ctl = (reg << 8) | val;
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_api.c1312 * @reg: 32bit register offset
1319 s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset, argument
1322 return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);

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