cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * CDDL HEADER START
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cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Common Development and Distribution License (the "License").
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * You may not use this file except in compliance with the License.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * or http://www.opensolaris.org/os/licensing.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * See the License for the specific language governing permissions
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * and limitations under the License.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * If applicable, add the following below this CDDL HEADER, with the
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying
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cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * CDDL HEADER END
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Use is subject to license terms.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * MII overrides for Marvell PHYs.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_PSC MII_VENDOR(0) /* PHY specific control */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_ASSERT_CRS_TX 0x0800 /* older PHYs */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_DOWNSHIFT_EN 0x0800 /* newer PHYs */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_RGMII_POWER_UP 0x0008 /* 88E1116, 88E1149 page 2 */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_POWER_DOWN 0x0004 /* 88E1116 page 0 */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_MODE_MASK 0x0380 /* 88E1112 page 2 */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore/* LED control page 3, 88E1116, 88E1149 */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_LED_LOS_CTRL(x) (((x) << 12) & MV_PSC_LED_LOS_MASK)
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_LED_INIT_CTRL(x) (((x) << 8) & MV_PSC_LED_INIT_MASK)
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_LED_STA1_CTRL(x) (((x) << 4) & MV_PSC_LED_STA1_MASK)
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_PSC_LED_STA0_CTRL(x) (((x)) & MV_PSC_LED_STA0_MASK)
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_INTEN MII_VENDOR(2) /* Interrupt enable */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_INTST MII_VENDOR(3) /* Interrupt status */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_EPSC MII_VENDOR(4) /* Ext. phy specific control */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_EADR MII_VENDOR(6) /* Extended address */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_LED_PSEL MII_VENDOR(6) /* 88E3016 */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MVPHY_EPSS MII_VENDOR(11) /* Ext. phy specific status */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_EPSS_FCAUTOSEL 0x8000 /* fiber/copper autosel */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore#define MV_EPSS_FCRESOL 0x1000 /* fiber/copper resol */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* enable class A driver for Yukon FE+ A0. */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* LED2 = ACT blink, LED1 = LINK), LED0 = SPEED */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* calibration, values not documented */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Normal BMCR reset now */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * The PHY apparently needs a soft reset, but supposedly
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * retains most of the other critical state.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* make sure that this PHY uses page 0 (copper) */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Disable energy detect mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore PHY_SET(ph, MVPHY_PSC, MV_PSC_RGMII_POWER_UP);
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Fix for signal amplitude in 10BASE-T, undocumented.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * This is from the Marvell reference source code.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * EC_U: IEEE A/B 1000BASE-T symmetry failure
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * EC_U is rev 0, Ultra 2 is rev 1 (at least the
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * unit I have), so we trigger on revid.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* page 3 is led control */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Weird... undocumented logic in the Intel e1000g driver.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * I'm not sure what these values really do.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* make sure that this PHY uses page 0 (copper) */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Disable energy detect mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore PHY_SET(ph, MVPHY_PSC, MV_PSC_RGMII_POWER_UP);
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* page 3 is led control */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Disable energy detect mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Disable energy detect mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* force TX CLOCK to 25 MHz */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore if (phy_read(ph, MVPHY_EPSS) & MV_EPSS_FCRESOL) {
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* interface indicates fiber */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Go into locked 1000BASE-X mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Disable energy detect mode */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore if (phy_read(ph, MVPHY_EPSS) & MV_EPSS_FCRESOL) {
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* interface indicates fiber */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* force TX CLOCK to 25 MHz */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Normal BMCR reset now */
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * If not autonegotiating, then we need to reset the PHY according to
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * Marvell. I don't think this is according to the spec. Apparently
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore * the register states are not lost during this.
cea606427170954e8cfcfa5417f3b60394180cb9Garrett D'Amore /* Unknown PHY model */