Lines Matching defs:reg
100 static uint32_t pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg);
101 static void pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg,
172 PCIE_DBG("SHPC Cfg reg 0x%02x: %08x\n", i,
261 uint32_t irq_locator, irq_serr_locator, reg;
280 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
282 if (reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) {
289 if (reg & PCI_HP_SERR_INT_ARBITER_IRQ) {
296 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
309 reg = pcishpc_read_reg(ctrl_p,
312 if (reg & PCI_HP_SLOT_PRESENCE_DETECTED)
317 if (reg & PCI_HP_SLOT_ISO_PWR_DETECTED)
322 if (reg & PCI_HP_SLOT_ATTN_DETECTED) {
340 if (reg & PCI_HP_SLOT_MRL_DETECTED)
344 if (reg & PCI_HP_SLOT_POWER_DETECTED)
350 reg);
1114 uint32_t reg;
1117 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
1120 reg &= ~PCI_HP_SERR_INT_MASK_ALL;
1122 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
1126 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
1127 if ((reg & PCI_HP_SLOT_STATE_MASK) == PCI_HP_SLOT_ENABLED) {
1128 reg &= ~(PCI_HP_SLOT_MASK_ALL |
1137 reg &= ~(PCI_HP_SLOT_MASK_ALL);
1141 pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
1160 uint32_t reg;
1163 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
1166 reg |= PCI_HP_SERR_INT_MASK_ALL;
1168 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
1172 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
1175 reg |= PCI_HP_SLOT_MASK_ALL;
1177 pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
1254 uint32_t reg;
1256 reg = pcishpc_read_reg(slot_p->hs_ctrl,
1261 reg & ~PCI_HP_SLOT_MRL_SERR_MASK);
1355 uint32_t reg;
1357 reg = pcishpc_read_reg(slot_p->hs_ctrl,
1362 reg | PCI_HP_SLOT_MRL_SERR_MASK);
1790 uint32_t reg;
1794 reg = pcishpc_read_reg(slot_p->hs_ctrl,
1798 slot_p->hs_info.cn_state = pcishpc_slot_shpc_to_hpc(reg);
1814 slot_p->hs_power_led_state = pcishpc_led_shpc_to_hpc((reg>>2)&3);
1817 slot_p->hs_attn_led_state = pcishpc_led_shpc_to_hpc((reg>>4)&3);
1835 uint32_t reg, cmd_code;
1840 reg = pcishpc_read_reg(slot_p->hs_ctrl,
1847 curr_state = pcishpc_slot_shpc_to_hpc(reg);
1856 if (slot_p->hs_power_led_state != pcishpc_led_shpc_to_hpc((reg>>2)&3)) {
1865 if (slot_p->hs_attn_led_state != pcishpc_led_shpc_to_hpc((reg>>4)&3)) {
2357 pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg)
2363 bus_p->bus_pci_hp_off + PCI_HP_DWORD_SELECT_OFF, (uint8_t)reg);
2367 PCI_HP_DWORD_SELECT_OFF) != (uint8_t)reg) {
2369 "select reg\n");
2385 pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg, uint32_t data)
2391 bus_p->bus_pci_hp_off + PCI_HP_DWORD_SELECT_OFF, (uint8_t)reg);
2395 PCI_HP_DWORD_SELECT_OFF) != (uint8_t)reg) {
2397 "DWORD select reg\n");
2424 uint32_t reg;
2436 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_I_REG);
2439 (reg & 31));
2442 ((reg>>8) & 31));
2445 ((reg>>16) & 31));
2448 ((reg>>24) & 31));
2450 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_II_REG);
2453 (reg & 31));
2455 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOT_CONFIGURATION_REG);
2457 numSlots = (reg & 31);
2463 ((reg>>8) & 31));
2466 ((reg>>16) & 0x7ff));
2469 ((reg>>29) & 0x1));
2472 (reg & PCI_HP_SLOT_CONFIG_MRL_SENSOR) ? "Yes" : "No");
2475 (reg & PCI_HP_SLOT_CONFIG_ATTN_BUTTON) ? "Yes" : "No");
2477 reg = pcishpc_read_reg(ctrl_p, PCI_HP_PROF_IF_SBCR_REG);
2479 switch (reg & 7) {
2503 ((reg>>16) &31));
2506 ((reg>>24) & 0xff));
2508 reg = pcishpc_read_reg(ctrl_p, PCI_HP_COMMAND_STATUS_REG);
2511 (reg & 0xff));
2514 ((reg>>8) & 31));
2517 ((reg>>16) & 1) ? "Yes" : "No");
2520 ((reg>>17) & 1) ? "Yes" : "No");
2523 ((reg>>18) & 1) ? "Yes" : "No");
2526 ((reg>>19) & 1) ? "Yes" : "No");
2528 reg = pcishpc_read_reg(ctrl_p, PCI_HP_IRQ_LOCATOR_REG);
2531 (reg & PCI_HP_IRQ_CMD_COMPLETE) ? "Yes" : "No");
2535 (reg & (PCI_HP_IRQ_SLOT_N_PENDING<<slot)) ? "Yes" : "No");
2538 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SERR_LOCATOR_REG);
2541 (reg & PCI_HP_IRQ_SERR_ARBITER_PENDING) ? "Yes" : "No");
2545 slot+1, (reg &
2549 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
2552 (reg & PCI_HP_SERR_INT_GLOBAL_IRQ_MASK) ? "Yes" : "No");
2555 (reg & PCI_HP_SERR_INT_GLOBAL_SERR_MASK) ? "Yes" : "No");
2558 (reg & PCI_HP_SERR_INT_CMD_COMPLETE_MASK) ? "Yes" : "No");
2561 (reg & PCI_HP_SERR_INT_ARBITER_SERR_MASK) ? "Yes" : "No");
2564 (reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) ? "Yes" : "No");
2567 (reg & PCI_HP_SERR_INT_ARBITER_IRQ) ? "Yes" : "No");
2573 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
2576 pcishpc_slot_textslotstate(pcishpc_slot_shpc_to_hpc(reg)));
2580 (reg>>2) &3)));
2584 (reg>>4)&3)));
2587 ((reg>>6)&1) ? "Fault Detected" : "No Fault");
2589 ((reg>>7)&1) ? "Depressed" : "Not Depressed");
2591 ((reg>>8)&1) ? "Not Closed" : "Closed");
2593 ((reg>>9)&1) ? "66mhz" : "33mgz");
2595 switch ((reg>>10)&3) {
2613 switch ((reg>>12)&3) {
2629 slot+1, (reg & PCI_HP_SLOT_PRESENCE_DETECTED) ? "Yes" :
2632 slot+1, (reg & PCI_HP_SLOT_ISO_PWR_DETECTED) ? "Yes" :
2635 slot+1, (reg & PCI_HP_SLOT_ATTN_DETECTED) ? "Yes" : "No");
2637 slot+1, (reg & PCI_HP_SLOT_MRL_DETECTED) ? "Yes" : "No");
2639 slot+1, (reg & PCI_HP_SLOT_POWER_DETECTED) ? "Yes" : "No");
2642 slot+1, (reg & PCI_HP_SLOT_PRESENCE_MASK) ? "Yes" : "No");
2644 slot+1, (reg & PCI_HP_SLOT_ISO_PWR_MASK) ? "Yes" : "No");
2646 slot+1, (reg & PCI_HP_SLOT_ATTN_MASK) ? "Yes" : "No");
2648 slot+1, (reg & PCI_HP_SLOT_MRL_MASK) ? "Yes" : "No");
2650 slot+1, (reg & PCI_HP_SLOT_POWER_MASK) ? "Yes" : "No");
2652 slot+1, (reg & PCI_HP_SLOT_MRL_SERR_MASK) ? "Yes" : "No");
2654 slot+1, (reg & PCI_HP_SLOT_POWER_SERR_MASK) ? "Yes" : "No");