/vbox/include/VBox/vmm/ |
H A D | tm.h | 85 VMM_INT_DECL(void) TMNotifyStartOfHalt(PVMCPU pVCpu); 86 VMM_INT_DECL(void) TMNotifyEndOfHalt(PVMCPU pVCpu); 93 VMM_INT_DECL(uint32_t) TMCalcHostTimerFrequency(PVM pVM, PVMCPU pVCpu); 103 VMM_INT_DECL(uint64_t) TMRealGet(PVM pVM); 104 VMM_INT_DECL(uint64_t) TMRealGetFreq(PVM pVM); 111 VMM_INT_DECL(uint64_t) TMVirtualGet(PVM pVM); 112 VMM_INT_DECL(uint64_t) TMVirtualGetNoCheck(PVM pVM); 113 VMM_INT_DECL(uint64_t) TMVirtualSyncGetLag(PVM pVM); 114 VMM_INT_DECL(uint32_t) TMVirtualSyncGetCatchUpPct(PVM pVM); 115 VMM_INT_DECL(uint64_ [all...] |
H A D | iem.h | 72 VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2, 75 VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp); 76 VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp); 80 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode, 82 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode, 84 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg); 85 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg); 86 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr); 87 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue); 88 VMM_INT_DECL(VBOXSTRICTR [all...] |
H A D | csam.h | 63 VMM_INT_DECL(bool) CSAMDoesPageNeedScanning(PVM pVM, RTRCUINTPTR GCPtr); 64 VMM_INT_DECL(bool) CSAMIsPageScanned(PVM pVM, RTRCPTR pPage); 65 VMM_INT_DECL(int) CSAMMarkPage(PVM pVM, RTRCUINTPTR pPage, bool fScanned); 66 VMM_INT_DECL(void) CSAMMarkPossibleCodePage(PVM pVM, RTRCPTR GCPtr); 67 VMM_INT_DECL(int) CSAMEnableScanning(PVM pVM); 68 VMM_INT_DECL(int) CSAMDisableScanning(PVM pVM); 69 VMM_INT_DECL(int) CSAMExecFault(PVM pVM, RTRCPTR pvFault); 70 VMM_INT_DECL(bool) CSAMIsKnownDangerousInstr(PVM pVM, RTRCUINTPTR GCPtr);
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H A D | em.h | 102 VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu); 103 VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState); 174 VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr); 175 VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, 177 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault); 178 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten); 179 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx, 183 VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); 186 VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); 187 VMM_INT_DECL(in [all...] |
H A D | ftm.h | 50 VMM_INT_DECL(bool) FTMIsDeltaLoadSaveActive(PVM pVM); 51 VMM_INT_DECL(int) FTMSetCheckpoint(PVM pVM, FTMCHECKPOINTTYPE enmType);
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H A D | hm.h | 141 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt); 142 VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM); 143 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu); 144 VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping); 145 VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable); 146 VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu); 147 VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu); 150 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu); 151 VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM); 152 VMM_INT_DECL(in [all...] |
H A D | gim.h | 173 VMM_INT_DECL(bool) GIMIsParavirtTscEnabled(PVM pVM); 174 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu); 175 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 176 VMM_INT_DECL(int) GIMXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis); 177 VMM_INT_DECL(bool) GIMShouldTrapXcptUD(PVMCPU pVCpu); 178 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 179 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
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H A D | patm.h | 145 VMM_INT_DECL(int) PATMReadPatchCode(PVM pVM, RTGCPTR GCPtrPatchCode, void *pvDst, size_t cbToRead, size_t *pcbRead); 147 VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTX pCtx); 148 VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTX pCtx, int rawRC); 149 VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTX pCtx); 150 VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTX pCtx, uint32_t efl); 151 VMM_INT_DECL(RCPTRTYPE(PPATMGCSTATE)) PATMGetGCState(PVM pVM); 152 VMM_INT_DECL(bool) PATMShouldUseRawMode(PVM pVM, RTRCPTR pAddrGC); 153 VMM_INT_DECL(int) PATMSetMMIOPatchInfo(PVM pVM, RTGCPHYS GCPhys, RTRCPTR pCachedData); 155 VMM_INT_DECL(bool) PATMIsInt3Patch(PVM pVM, RTRCPTR pInstrGC, uint32_t *pOpcode, uint32_t *pSize); 156 VMM_INT_DECL(boo [all...] |
H A D | pdmapi.h | 45 VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM); 46 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc); 47 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc); 48 VMM_INT_DECL(bool) PDMHasApic(PVM pVM); 49 VMM_INT_DECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending); 54 VMM_INT_DECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value); 55 VMM_INT_DECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value); 56 VMM_INT_DECL(int) PDMApicGetTimerFreq(PVM pVM, uint64_t *pu64Value); 57 VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys); 58 VMM_INT_DECL(boo [all...] |
H A D | vmm.h | 260 VMM_INT_DECL(RTRCPTR) VMMGetStackRC(PVMCPU pVCpu); 266 VMM_INT_DECL(uint32_t) VMMGetSvnRev(void); 267 VMM_INT_DECL(VMMSWITCHER) VMMGetSwitcher(PVM pVM); 268 VMM_INT_DECL(bool) VMMIsInRing3Call(PVMCPU pVCpu); 269 VMM_INT_DECL(void) VMMTrashVolatileXMMRegs(void); 270 VMM_INT_DECL(int) VMMPatchHypercall(PVM pVM, void *pvBuf, size_t cbBuf, size_t *pcbWritten); 271 VMM_INT_DECL(void) VMMHypercallsEnable(PVMCPU pVCpu); 272 VMM_INT_DECL(void) VMMHypercallsDisable(PVMCPU pVCpu);
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/vbox/src/VBox/VMM/VMMAll/ |
H A D | TMAllReal.cpp | 35 VMM_INT_DECL(uint64_t) TMRealGet(PVM pVM) 48 VMM_INT_DECL(uint64_t) TMRealGetFreq(PVM pVM)
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H A D | FTMAll.cpp | 41 VMM_INT_DECL(int) FTMSetCheckpoint(PVM pVM, FTMCHECKPOINTTYPE enmType) 61 VMM_INT_DECL(bool) FTMIsDeltaLoadSaveActive(PVM pVM)
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H A D | HMAll.cpp | 88 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt) 112 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu) 215 VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCPtr) 248 VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM) 283 VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM) 299 VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM) 314 VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM) 327 VMM_INT_DECL(bool) HMAreMsrBitmapsAvailable(PVM pVM) 350 VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM) 369 VMM_INT_DECL(in [all...] |
H A D | GIMAll.cpp | 64 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu) 91 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) 124 VMM_INT_DECL(bool) GIMIsParavirtTscEnabled(PVM pVM) 153 VMM_INT_DECL(bool) GIMShouldTrapXcptUD(PVMCPU pVCpu) 178 VMM_INT_DECL(int) GIMXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis) 206 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 241 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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H A D | DBGFAll.cpp | 36 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM) 67 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM) 81 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM) 95 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM) 109 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM) 123 VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM) 139 VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM) 177 VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue) 263 VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
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H A D | CSAMAll.cpp | 54 VMM_INT_DECL(int) CSAMExecFault(PVM pVM, RTRCPTR pvFault) 82 VMM_INT_DECL(bool) CSAMIsPageScanned(PVM pVM, RTRCPTR pPage) 111 VMM_INT_DECL(int) CSAMMarkPage(PVM pVM, RTRCUINTPTR pPage, bool fScanned) 181 VMM_INT_DECL(bool) CSAMDoesPageNeedScanning(PVM pVM, RTRCUINTPTR GCPtr) 205 VMM_INT_DECL(void) CSAMMarkPossibleCodePage(PVM pVM, RTRCPTR GCPtr) 223 VMM_INT_DECL(int) CSAMEnableScanning(PVM pVM) 236 VMM_INT_DECL(int) CSAMDisableScanning(PVM pVM) 254 VMM_INT_DECL(bool) CSAMIsKnownDangerousInstr(PVM pVM, RTRCUINTPTR GCPtr)
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H A D | GIMAllKvm.cpp | 46 VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) 126 VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu) 141 VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM) 167 VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 214 VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue) 328 VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu) 343 VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
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H A D | VMMAll.cpp | 179 VMM_INT_DECL(RTRCPTR) VMMGetStackRC(PVMCPU pVCpu) 342 VMM_INT_DECL(uint32_t) VMMGetSvnRev(void) 354 VMM_INT_DECL(VMMSWITCHER) VMMGetSwitcher(PVM pVM) 367 VMM_INT_DECL(bool) VMMIsInRing3Call(PVMCPU pVCpu) 407 VMM_INT_DECL(int) VMMPatchHypercall(PVM pVM, void *pvBuf, size_t cbBuf, size_t *pcbWritten) 443 VMM_INT_DECL(void) VMMHypercallsEnable(PVMCPU pVCpu) 458 VMM_INT_DECL(void) VMMHypercallsDisable(PVMCPU pVCpu)
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H A D | PDMAll.cpp | 164 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc) 186 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc) 207 VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM) 219 VMM_INT_DECL(bool) PDMHasApic(PVM pVM) 286 VMM_INT_DECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending) 367 VMM_INT_DECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value) 387 VMM_INT_DECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value) 406 VMM_INT_DECL(int) PDMApicGetTimerFreq(PVM pVM, uint64_t *pu64Value) 470 VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys) 490 VMM_INT_DECL(boo [all...] |
H A D | GIMAllHv.cpp | 44 VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) 62 VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu) 75 VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM) 93 VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 183 VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
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H A D | PATMAll.cpp | 51 VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTX pCtx) 127 VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTX pCtx, int rawRC) 224 VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTX pCtx) 241 VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTX pCtx, uint32_t efl) 256 VMM_INT_DECL(bool) PATMShouldUseRawMode(PVM pVM, RTRCPTR pAddrGC) 269 VMM_INT_DECL(RCPTRTYPE(PPATMGCSTATE)) PATMGetGCState(PVM pVM) 318 VMM_INT_DECL(int) PATMReadPatchCode(PVM pVM, RTGCPTR GCPtrPatchCode, void *pvDst, size_t cbToRead, size_t *pcbRead) 376 VMM_INT_DECL(int) PATMSetMMIOPatchInfo(PVM pVM, RTGCPHYS GCPhys, RTRCPTR pCachedData) 396 VMM_INT_DECL(bool) PATMAreInterruptsEnabled(PVM pVM) 413 VMM_INT_DECL(boo [all...] |
H A D | TMAllCpu.cpp | 233 VMM_INT_DECL(bool) TMCpuTickCanUseRealTSC(PVM pVM, PVMCPU pVCpu, uint64_t *poffRealTsc, bool *pfParavirtTsc) 344 VMM_INT_DECL(uint64_t) TMCpuTickGetDeadlineAndTscOffset(PVM pVM, PVMCPU pVCpu, uint64_t *poffRealTsc, 449 VMM_INT_DECL(uint64_t) TMCpuTickGetNoCheck(PVMCPU pVCpu) 465 VMM_INT_DECL(int) TMCpuTickSet(PVM pVM, PVMCPU pVCpu, uint64_t u64Tick) 495 VMM_INT_DECL(int) TMCpuTickSetLastSeen(PVMCPU pVCpu, uint64_t u64LastSeenTick) 513 VMM_INT_DECL(uint64_t) TMCpuTickGetLastSeen(PVMCPU pVCpu) 552 VMM_INT_DECL(bool) TMCpuTickIsTicking(PVMCPU pVCpu)
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H A D | TMAllVirtual.cpp | 267 VMM_INT_DECL(uint64_t) TMVirtualGet(PVM pVM) 284 VMM_INT_DECL(uint64_t) TMVirtualGetNoCheck(PVM pVM) 752 VMM_INT_DECL(uint64_t) TMVirtualSyncGet(PVM pVM) 767 VMM_INT_DECL(uint64_t) TMVirtualSyncGetNoCheck(PVM pVM) 782 VMM_INT_DECL(uint64_t) TMVirtualSyncGetEx(PVM pVM, bool fCheckTimers) 799 VMM_INT_DECL(uint64_t) TMVirtualSyncGetWithDeadlineNoCheck(PVM pVM, uint64_t *pcNsToDeadline) 830 VMM_INT_DECL(uint64_t) TMVirtualSyncGetLag(PVM pVM) 842 VMM_INT_DECL(uint32_t) TMVirtualSyncGetCatchUpPct(PVM pVM) 856 VMM_INT_DECL(uint64_t) TMVirtualGetFreq(PVM pVM) 914 VMM_INT_DECL(uint64_ [all...] |
/vbox/src/VBox/VMM/include/ |
H A D | GIMKvmInternal.h | 258 VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM); 259 VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu); 260 VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 261 VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 262 VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue); 263 VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu); 264 VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
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H A D | GIMHvInternal.h | 525 VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM); 526 VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu); 527 VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 528 VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 529 VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
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