0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * GIM - Guest Interface Manager, KVM, All Contexts.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * Copyright (C) 2015 Oracle Corporation
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * available from http://www.virtualbox.org. This file is free software;
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * you can redistribute it and/or modify it under the terms of the GNU
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * General Public License (GPL) as published by the Free Software
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync/*******************************************************************************
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync* Header Files *
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync*******************************************************************************/
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * Handles the KVM hypercall.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @returns VBox status code.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pVCpu Pointer to the VMCPU.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pCtx Pointer to the guest-CPU context.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsyncVMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Get the hypercall operation and arguments.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Verify that guest ring-0 is the one making the hypercall.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Do the work.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync PVMCPU pVCpuTarget = &pVM->aCpus[uHyperArg1]; /** ASSUMES pVCpu index == ApicId of the VCPU. */
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync int rc2 = SUPR3CallVMMR0(pVM->pVMR0, pVCpuTarget->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL);
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Place the result in rax/eax.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * Returns whether the guest has configured and enabled the use of KVM's
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * hypercall interface.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @returns true if hypercalls are enabled, false otherwise.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pVCpu Pointer to the VMCPU.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsyncVMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync /* KVM paravirt interface doesn't have hypercall control bits like Hyper-V does
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync that guests can control. It's always enabled. */
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync return true;
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * Returns whether the guest has configured and enabled the use of KVM's
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * paravirtualized TSC.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @returns true if paravirt. TSC is enabled, false otherwise.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pVM Pointer to the VM.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsyncVMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM)
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync return true;
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync return false;
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * MSR read handler for KVM.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @returns Strict VBox status code like CPUMQueryGuestMsr().
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @retval VINF_CPUM_R3_MSR_READ
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @retval VERR_CPUM_RAISE_GP_0
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pVCpu Pointer to the VMCPU.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param idMsr The MSR being read.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pRange The range this MSR belongs to.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param puValue Where to store the MSR value read.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsyncVMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * MSR write handler for KVM.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @returns Strict VBox status code like CPUMSetGuestMsr().
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @retval VINF_CPUM_R3_MSR_WRITE
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @retval VERR_CPUM_RAISE_GP_0
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pVCpu Pointer to the VMCPU.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param idMsr The MSR being written.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param pRange The range this MSR belongs to.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync * @param uRawValue The raw value with the ignored bits not masked.
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsyncVMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync /* Is the system-time struct. already enabled? If so, get flags that need preserving. */
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync && MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync fFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync /* Enable and populate the system-time struct. */
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync pKvmCpu->u32SystemTimeVersion = pKvmCpu->u32SystemTimeVersion + 2;
6fd7ca38c2e6dbc9871b33b11cf70ed6bf4e7d03vboxsync int rc = gimR3KvmEnableSystemTime(pVM, pVCpu, pKvmCpu, fFlags);
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync#endif /* IN_RING3 */
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync /* Enable the wall-clock struct. */
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock, uVersion);
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync#endif /* IN_RING3 */
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
0bc35f54322c5f9b2d43b064f839a8cf8c99a234vboxsync LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Whether we need to trap #UD exceptions in the guest.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * the Intel VMCALL instruction to make hypercalls and we need to trap and
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * optionally patch them to the AMD-V VMMCALL instruction and handle the
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * hypercall.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * I guess this was done so that guest teleporation between an AMD and an Intel
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * machine would working without any changes at the time of teleporation.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * However, this also means we -always- need to intercept #UD exceptions on one
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * of the two CPU models (Intel or AMD). Hyper-V solves this problem more
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * elegantly by letting the hypervisor supply an opaque hypercall page.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * For raw-mode VMs, this function will always return true. See gimR3KvmInit().
66d96ba0c4c722996a3a1e6d92403a14a27db1b4vboxsync * @param pVCpu Pointer to the VMCPU.
66d96ba0c4c722996a3a1e6d92403a14a27db1b4vboxsyncVMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu)
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * Exception handler for #UD.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * @param pVCpu Pointer to the VMCPU.
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * @param pCtx Pointer to the guest-CPU context.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * @param pDis Pointer to the disassembled instruction state at RIP.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Optional, can be NULL.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsyncVMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
9c178a84047ec38c02debb747cbdc7de4531d940vboxsync * If we didn't ask for #UD to be trapped, bail.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Make sure guest ring-0 is the one making the hypercall.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Disassemble the instruction at RIP to figure out if it's the Intel
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * VMCALL instruction and if so, handle it as a hypercall.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Patch the instruction to so we don't have to spend time disassembling it each time.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync if ( pDis->pCurInstr->uOpcode != pKvm->uOpCodeNative
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync rc = VMMPatchHypercall(pVM, &abHypercall, sizeof(abHypercall), &cbWritten);
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, &abHypercall, sizeof(abHypercall));
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * Perform the hypercall and update RIP.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * For HM, we can simply resume guest execution without perform the hypercall now and
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * For raw-mode we need to do this now anyway. So we do it here regardless with an added
fa35e2dfd910e18dbb7f136bfe56030e5116d51cvboxsync * advantage is that it saves one world-switch for the HM case.