Searched refs:MII_BMCR (Results 1 - 10 of 10) sorted by relevance

/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dmv88e1xxx.c79 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
82 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
157 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
172 (void) simple_mdio_write(phy, MII_BMCR, ctl);
193 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
196 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
214 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
216 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
222 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
261 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBAC
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H A Dch_compat.h44 #ifndef MII_BMCR
47 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro
H A Drtl8139.c105 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, enumerator in enum:RTL8139_registers
213 fullduplex = inw(nic->ioaddr + MII_BMCR) & BMCRDuplex;
H A Dtg3.c278 err = tg3_writephy(tp, MII_BMCR, phy_control);
284 err = tg3_readphy(tp, MII_BMCR, &phy_control);
424 tg3_writephy(tp, MII_BMCR,
649 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
771 tg3_readphy(tp, MII_BMCR, &bmcr);
772 tg3_readphy(tp, MII_BMCR, &bmcr);
1221 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2503 err |= tg3_writephy(tp, MII_BMCR,
H A Dsundance.c698 mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl);
725 mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR);
H A Dforcedeth.c369 #define MII_BMCR 0x00 /* Basic mode control register */ macro
H A Dtg3.h80 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/illumos-gate/usr/src/uts/common/io/cxgbe/t4nex/
H A Dosdep.h47 #define MII_BMCR 0x00 macro
/illumos-gate/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h123 #define MII_BMCR 0x00 /* Basic mode control register */ macro

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