/* $Id: tg3.c,v 1.5 2003/03/19 21:26:20 gbaum Exp $
* tg3.c: Broadcom Tigon3 ethernet driver.
*
* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
* Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
* Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com) [etherboot port]
*/
/* 11-13-2003 timlegge Fix Issue with NetGear GA302T
* 11-18-2003 ebiederm Generalize NetGear Fix to what the code was supposed to be.
*/
#include "etherboot.h"
#include "nic.h"
#include "pci.h"
#include "timer.h"
/*#include "string.h"*/
#include "tg3.h"
/* Dummy defines for error handling */
/* These numbers seem to be hard coded in the NIC firmware somehow.
* You can't change the ring sizes, but you can change where you place
* them in the NIC onboard memory.
*/
/* (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
512 : 1024) */
static struct bss {
} tg3_bss;
/**
* pci_save_state - save the PCI configuration space of a device before suspending
* @dev: - PCI device that we're dealing with
* @buffer: - buffer to hold config space context
*
* @buffer must be large enough to hold the entire PCI 2.2 config space
* (>= 64 bytes).
*/
{
int i;
for (i = 0; i < 16; i++)
return 0;
}
/**
* pci_restore_state - Restore the saved state of a PCI device
* @dev: - PCI device that we're dealing with
* @buffer: - saved PCI config space
*
*/
{
int i;
for (i = 0; i < 16; i++)
return 0;
}
{
}
{
udelay(100);
}
{
}
{
/* Always leave this as zero. */
}
{
/* Always leave this as zero. */
}
{
}
{
(orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
clock_ctrl | (CLOCK_CTRL_ALTCLK));
}
}
{
*val = 0xffffffff;
while (loops-- > 0) {
udelay(10);
if ((frame_val & MI_COM_BUSY) == 0) {
udelay(5);
break;
}
}
if (loops > 0) {
ret = 0;
}
return ret;
}
{
while (loops-- > 0) {
udelay(10);
if ((frame_val & MI_COM_BUSY) == 0) {
udelay(5);
break;
}
}
if (loops > 0)
ret = 0;
return ret;
}
{
int err;
return err;
}
{
return;
}
{
/* OK, reset it, and poll the BMCR_RESET bit until it
* clears or we time out.
*/
if (err != 0)
return -EBUSY;
limit = 5000;
while (limit--) {
if (err != 0)
return -EBUSY;
if ((phy_control & BMCR_RESET) == 0) {
udelay(40);
break;
}
udelay(10);
}
if (limit <= 0)
return -EBUSY;
return 0;
}
{
while (limit--) {
if ((tmp32 & 0x1000) == 0)
break;
}
if (limit <= 0)
return -EBUSY;
return 0;
}
{
{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
};
int chan;
int i;
for (i = 0; i < 6; i++)
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
for (i = 0; i < 6; i += 2) {
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
low &= 0x7fff;
high &= 0x000f;
return -EBUSY;
}
}
}
return 0;
}
{
int chan;
int i;
for (i = 0; i < 6; i++)
if (tg3_wait_macro_done(tp))
return -EBUSY;
}
return 0;
}
{
retries = 10;
do_phy_reset = 1;
do {
if (do_phy_reset) {
if (err)
return err;
do_phy_reset = 0;
}
/* Disable transmitter and interrupt. */
reg32 |= 0x3000;
/* Set full-duplex, 1000 mbps. */
/* Set to master mode. */
/* Enable SM_DSP_CLOCK and 6dB. */
/* Block the PHY control access. */
if (!err)
break;
} while (--retries);
if (err)
return err;
reg32 &= ~0x3000;
return err;
}
/* This will reset the tigon3 PHY if there is no valid
* link.
*/
{
int err;
if (err != 0)
return -EBUSY;
if (err)
return err;
goto out;
}
if (err)
return err;
out:
return 0;
}
{
/* Make sure register accesses (indirect or otherwise)
* will function correctly.
*/
power_control |= 0;
return;
}
{
if (!tp->carrier_ok) {
printf("Link is down.\n");
} else {
printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
1000 :
100 : 10)),
"full" : "half"),
}
}
#else
#endif
{
if (local_adv & ADVERTISE_PAUSE_CAP) {
if (local_adv & ADVERTISE_PAUSE_ASYM) {
if (remote_adv & LPA_PAUSE_CAP)
else if (remote_adv & LPA_PAUSE_ASYM)
} else {
if (remote_adv & LPA_PAUSE_CAP)
}
} else if (local_adv & ADVERTISE_PAUSE_ASYM) {
if ((remote_adv & LPA_PAUSE_CAP) &&
(remote_adv & LPA_PAUSE_ASYM))
}
if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
else
if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
else
}
static void tg3_aux_stat_to_speed_duplex(
{
};
}
{
}
}
}
}
}
new_adv = 0;
}
}
}
} else {
}
return 0;
}
{
int err;
/* Turn off tap power management. */
udelay(40);
return err;
}
{
int current_link_up;
int i, err;
/* Some third-party PHYs need to be reset on link going
* down.
*/
(tp->carrier_ok)) {
if (!(bmsr & BMSR_LSTATUS))
}
bmsr = 0;
if (!(bmsr & BMSR_LSTATUS)) {
if (err)
return err;
for (i = 0; i < 1000; i++) {
udelay(10);
if (bmsr & BMSR_LSTATUS) {
udelay(40);
break;
}
}
!(bmsr & BMSR_LSTATUS) &&
if (!err)
if (err)
return err;
}
}
/* 5701 {A0,B0} CRC bug workaround */
}
/* Clear pending interrupts... */
else
current_link_up = 0;
if (bmsr & BMSR_LSTATUS) {
for (i = 0; i < 2000; i++) {
udelay(10);
if (aux_stat)
break;
}
if (bmcr & BMCR_ANENABLE) {
current_link_up = 1;
/* Force autoneg restart if we are exiting
* low power mode.
*/
if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
current_link_up = 0;
}
} else {
current_link_up = 0;
}
}
if (current_link_up == 1 &&
/* If we are not advertising full pause capability,
* something is wrong. Bring the link down and reconfigure.
*/
if (local_adv != ADVERTISE_PAUSE_CAP) {
current_link_up = 0;
} else {
}
}
if (current_link_up == 0) {
if (tmp & BMSR_LSTATUS)
current_link_up = 1;
}
if (current_link_up == 1) {
else
} else
(current_link_up == 1 &&
} else {
if (current_link_up == 1)
}
/* ??? Without this setting Netgear GA302T PHY does not
* With this other PHYs cannot bring up the link
*/
}
/* Link change polled. */
tw32_carefully(MAC_EVENT, 0);
current_link_up == 1 &&
udelay(120);
}
}
return 0;
}
#else
#endif /* SUPPORT_COPPER_PHY */
struct tg3_fiber_aneginfo {
int state;
#define ANEG_STATE_UNKNOWN 0
int ability_match_count;
};
#define ANEG_OK 0
struct tg3_fiber_aneginfo *ap)
{
unsigned long delta;
int ret;
ap->ability_match_cfg = 0;
ap->ability_match_count = 0;
ap->ability_match = 0;
ap->idle_match = 0;
}
ap->ability_match = 0;
ap->ability_match_count = 0;
} else {
}
}
if (rx_cfg_reg & ANEG_CFG_ACK)
else
ap->idle_match = 0;
} else {
ap->ability_match_cfg = 0;
ap->ability_match_count = 0;
ap->ability_match = 0;
rx_cfg_reg = 0;
}
case ANEG_STATE_UNKNOWN:
/* fallthru */
case ANEG_STATE_AN_ENABLE:
ap->ability_match_cfg = 0;
ap->ability_match_count = 0;
ap->ability_match = 0;
ap->idle_match = 0;
} else {
}
break;
case ANEG_STATE_RESTART_INIT:
tw32(MAC_TX_AUTO_NEG, 0);
/* fallthru */
case ANEG_STATE_RESTART:
if (delta > ANEG_STATE_SETTLE_TIME) {
} else {
}
break;
break;
break;
}
break;
/* fallthru */
case ANEG_STATE_ACK_DETECT:
} else {
}
} else if (ap->ability_match != 0 &&
}
break;
ret = ANEG_FAILED;
break;
}
MR_NP_RX);
break;
case ANEG_STATE_COMPLETE_ACK:
if (ap->ability_match != 0 &&
break;
}
if (delta > ANEG_STATE_SETTLE_TIME) {
} else {
} else {
ret = ANEG_FAILED;
}
}
}
break;
break;
case ANEG_STATE_IDLE_DETECT:
if (ap->ability_match != 0 &&
break;
}
if (delta > ANEG_STATE_SETTLE_TIME) {
/* XXX another gem from the Broadcom driver :( */
}
break;
case ANEG_STATE_LINK_OK:
break;
/* ??? unimplemented */
break;
/* ??? unimplemented */
break;
default:
ret = ANEG_FAILED;
break;
};
return ret;
}
{
int current_link_up;
int i;
/* Reset when initting first time or we have a link. */
/* Set PLL lock range. */
/* SW reset */
/* Wait for reset to complete. */
mdelay(5);
/* Enable auto-lock and comdet, select txclk for tx. */
/* Assert and deassert POR. */
udelay(40);
udelay(40);
/* Wait for signal to stabilize */
mdelay(150);
/* Deselect the channel register so we can read the PHYID
* later.
*/
}
/* Disable link change interrupt. */
tw32_carefully(MAC_EVENT, 0);
current_link_up = 0;
unsigned int tick;
tw32(MAC_TX_AUTO_NEG, 0);
tick = 0;
while (++tick < 195000) {
status == ANEG_FAILED)
break;
udelay(1);
}
(MR_AN_COMPLETE | MR_LINK_OK |
remote_adv = 0;
current_link_up = 1;
}
for (i = 0; i < 60; i++) {
udelay(20);
if ((tr32(MAC_STATUS) &
MAC_STATUS_CFG_CHANGED)) == 0)
break;
}
if (current_link_up == 0 &&
current_link_up = 1;
}
} else {
/* Forcing 1000FD link up. */
current_link_up = 1;
}
}
for (i = 0; i < 100; i++) {
udelay(20);
if ((tr32(MAC_STATUS) &
MAC_STATUS_CFG_CHANGED)) == 0)
break;
}
current_link_up = 0;
if (current_link_up == 1) {
} else {
}
} else {
if (orig_pause_cfg != now_pause_cfg ||
}
}
}
return 0;
}
#else
#endif /* SUPPORT_FIBER_PHY */
{
int err;
} else {
}
((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT) |
(0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
else
((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT) |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
return err;
}
/* To stop a block, clear the enable bit and poll till it
* clears.
*/
{
unsigned int i;
switch(ofs) {
case RCVLSC_MODE:
case DMAC_MODE:
case MBFREE_MODE:
case BUFMGR_MODE:
case MEMARB_MODE:
* 5705, just say success.
*/
return 0;
default:
break;
}
}
val &= ~enable_bit;
for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100);
if ((val & enable_bit) == 0)
break;
}
if (i == MAX_WAIT_CNT) {
printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
ofs, enable_bit);
return -ENODEV;
}
return 0;
}
{
int i, err;
if (err)
goto out;
for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100);
break;
}
if (i >= MAX_WAIT_CNT) {
printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
tr32(MAC_TX_MODE));
return -ENODEV;
}
if (err)
goto out;
out:
return err;
}
{
/* Force NVRAM to settle.
* This deals with a chip bug which can result in EEPROM
* corruption.
*/
int i;
for (i = 0; i < 100000; i++) {
break;
udelay(10);
}
}
}
/* In Etherboot we don't need to worry about the 5701
* REG_WRITE_BUG because we do all register writes indirectly.
*/
/* do the reset */
/* Flush PCI posted writes. The normal MMIO registers
* are inaccessible at this time so this is the only
* way to make this reliably. I tried to use indirect
*/
udelay(120);
/* Re-enable indirect register accesses. */
tp->misc_host_ctrl);
/* Set MAX PCI retry to zero. */
/* Make sure PCI-X relaxed ordering bit is clear. */
tp->pci_clock_ctrl |=
}
}
{
int i;
/* Wait for RX cpu to ACK the event. */
for (i = 0; i < 100; i++) {
break;
udelay(1);
}
}
}
{
int i;
/* Wait for firmware initialization to complete. */
for (i = 0; i < 100000; i++) {
break;
udelay(10);
}
if (i >= 100000 &&
printf("Firmware will not restart magic=%x\n",
val);
return -ENODEV;
}
}
return 0;
}
{
}
{
int i;
for (i = 0; i < 4; i++) {
}
for(i = 0; i < 12; i++) {
}
}
}
{
}
}
{
unsigned i;
/* Zero out the tg3 variables */
*
* The chip has been shut down and the driver detached from
* the networking, so no interrupts or new tx packets will
* end up in the driver.
*/
/* Initialize invariants of the rings, we only set this
* stuff once. This works because the card does not
* write into the rx buffer posting rings.
*/
for (i = 0; i < TG3_RX_RING_SIZE; i++) {
/* Note where the receive buffer for the ring is placed */
}
}
do { \
} \
} while(0)
/* initialize/reset the tg3 */
{
/* Simply don't support setups with extremly buggy firmware in etherboot */
printf("Error 5701_A0 firmware bug detected\n");
return -EINVAL;
}
/* Originally this was all in tg3_init_hw */
/* Force the chip into D0. */
/* Originally this was all in tg3_reset_hw */
/* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
if (err)
return err;
}
/* This works around an issue with Athlon chipsets on
* B3 tigon3 silicon. This bit has no effect on any
* other revision.
*/
}
/* Descriptor ring init may make accesses to the
* NIC SRAM area to setup the TX descriptors, so we
* can only do this after the hardware has been
* successfully reset.
*/
/* Clear statistics/status block in chip */
for (i = NIC_SRAM_STATS_BLK;
i += sizeof(uint32_t)) {
tg3_write_mem(i, 0);
udelay(40);
}
}
/* This value is determined during the probe time DMA
* engine test, tg3_setup_dma.
*/
/* Setup the timer prescalar register. Clock is always 66Mhz. */
(65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
else
}
} else {
}
for (i = 0; i < 2000; i++) {
break;
udelay(10);
}
if (i >= 2000) {
printf("tg3_setup_hw cannot enable BUFMGR\n");
return -ENODEV;
}
for (i = 0; i < 2000; i++) {
break;
udelay(10);
}
if (i >= 2000) {
printf("tg3_setup_hw cannot reset FTQ\n");
return -ENODEV;
}
/* Initialize TG3_BDINFO's at:
* RCVDBDI_STD_BD: standard eth size rx ring
* RCVDBDI_JUMBO_BD: jumbo frame rx ring
* RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
*
* like so:
* TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
* ring attribute flags
* TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
*
* Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
* Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
*
* ??? No space allocated for mini receive ring? :(
*
* The size of each ring is fixed in the firmware, but the location is
* configurable.
*/
{
/* Setup replenish thresholds. */
/* Etherboot lives below 4GB */
};
/* Buffer maximum length */
/* Disable the mini frame rx ring */
/* Disable the jumbo frame rx ring */
};
} else {
}
}
/* There is only one send ring on 5705, no need to explicitly
* disable the others.
*/
/* Clear out send RCB ring in SRAM. */
}
/* There is only one receive return ring on 5705, no need to explicitly
* disable the others.
*/
}
}
tp->rx_rcb_ptr = 0;
0);
tp->rx_std_ptr);
/* Initialize MAC address and backoff seed. */
/* Calculate RDMAC_MODE setting early, we need it to determine
* the RCVLPC_STATE_ENABLE mask.
*/
}
}
}
/* Setup host coalescing engine. */
tw32(HOSTCC_MODE, 0);
for (i = 0; i < 2000; i++) {
break;
udelay(10);
}
}
}
}
}
{
/* MTU + ethernet header + FCS + optional VLAN tag */
/* The slot time is changed by tg3_setup_phy if we
* run at gigabit with half duplex.
*/
(2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT) |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT),
/* Receive rules. */
RCVLPC_CONFIG, 0x0181,
RCVLPC_STATS_ENABLE, 0xffffff,
SNDDATAI_STATSENAB, 0xffffff,
/* Host coalescing engine */
/* Status/statistics block address. */
/* Etherboot lives below 4GB, so HIGH == 0 */
/* No need to enable 32byte coalesce mode. */
/* Accept all multicast frames. */
MAC_HASH_REG_0, 0xffffffff,
MAC_HASH_REG_1, 0xffffffff,
MAC_HASH_REG_2, 0xffffffff,
MAC_HASH_REG_3, 0xffffffff,
};
/* Host coalescing engine */
/* Status/statistics block address. */
/* Etherboot lives below 4GB, so HIGH == 0 */
};
}
}
tw32(MAC_LED_CTRL, 0);
}
/* Prevent chip from dropping frames when flow control
* is enabled.
*/
/* Ignore CRC stats */
/* Initialize receive rules. */
limit = 8;
else
limit = 16;
limit -= 4;
switch (limit) {
case 4: /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
case 3: /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
case 2:
case 1:
default:
break;
};
return err;
}
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
{
mdelay(1);
/* Enable seeprom accesses. */
if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
} else {
}
} else {
}
}
static int tg3_nvram_read_using_eeprom(
{
int i;
if (offset > EEPROM_ADDR_ADDR_MASK ||
(offset % 4) != 0) {
return -EINVAL;
}
tmp |
(0 << EEPROM_ADDR_DEVID_SHIFT) |
((offset << EEPROM_ADDR_ADDR_SHIFT) &
for (i = 0; i < 10000; i++) {
if (tmp & EEPROM_ADDR_COMPLETE)
break;
udelay(100);
}
if (!(tmp & EEPROM_ADDR_COMPLETE)) {
return -EBUSY;
}
return 0;
}
{
int i, saw_done_clear;
if (offset > NVRAM_ADDR_MSK)
return -EINVAL;
for (i = 0; i < 1000; i++) {
break;
udelay(20);
}
/* Wait for done bit to clear then set again. */
saw_done_clear = 0;
for (i = 0; i < 1000; i++) {
udelay(10);
if (!saw_done_clear &&
saw_done_clear = 1;
else if (saw_done_clear &&
break;
}
if (i >= 1000) {
return -EBUSY;
}
return 0;
}
struct subsys_tbl_ent {
};
/* Broadcom boards. */
/* 3com boards. */
/* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX }, 3C996CT */
/* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX }, 3C997T */
/* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX }, 3C997SZ */
/* DELL boards. */
/* Compaq boards. */
};
{
unsigned i;
for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
break;
}
}
if (val == NIC_SRAM_DATA_SIG_MAGIC) {
if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
} else {
if (nic_phy_id != 0) {
}
}
switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
break;
break;
default:
break;
};
}
}
/* Now read the physical PHY_ID from the chip and verify
* that it is sane. If it doesn't look good, we fall back
* to either the hard-coded table based PHY_ID and failing
* that the value found in the eeprom area.
*/
} else {
/* phy_id currently holds the value found in the
* subsys_id_to_phy_id[] table or PHY_ID_INVALID
* if a match was not found there.
*/
if (!eeprom_signature_found ||
return -ENODEV;
}
}
if (err)
return err;
/* These chips, when reset, only advertise 10Mb
* capabilities. Fix that.
*/
mii_tg3_ctrl = 0;
(BMCR_ANRESTART | BMCR_ANENABLE));
}
}
}
/* Enable Ethernet@WireSpeed */
}
/* Determine the PHY led mode.
* Be careful if this gets set wrong it can result in an inability to
* establish a link.
*/
}
} else {
if (eeprom_signature_found &&
}
return err;
}
{
int i;
for (i = 0; i < 256; i += 4) {
goto out_not_found;
}
/* Now parse and find the part number. */
for (i = 0; i < 256; ) {
int block_end;
i = (i + 3 +
(vpd_data[i + 1] +
continue;
}
if (val != 0x90)
goto out_not_found;
block_end = (i + 3 +
(vpd_data[i + 1] +
i += 3;
while (i < block_end) {
if (vpd_data[i + 0] == 'P' &&
if (partno_len > 24)
goto out_not_found;
&vpd_data[i + 3],
/* Success. */
return;
}
}
/* Part number not found. */
goto out_not_found;
}
}
#else
#endif
{
int err;
/* Read the subsystem vendor and device ids */
/* The sun_5704 code needs infrastructure etherboot does have
* ignore it for now.
*/
* reordering to the mailbox registers done by the host
* controller can cause major troubles. We read back from
* every mailbox register write to force the writes to be
* posted to the chip in order.
*
* TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
*/
/* Force memory write invalidate off. If we leave it on,
* then on 5700_BX chips we have to enable a workaround.
* The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
* to match the cacheline size. The Broadcom driver have this
* workaround but turns MWI off all the times so never uses
* it. This seems to suggest that the workaround is insufficient.
*/
/* Also, force SERR#/PERR# in PCI command. */
/* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
* has the register indirect write enable bit set before
* we try to access any of the MMIO registers. It is also
* critical that the PCI-X hw workaround situation is decided
* before that as well.
*/
/* Initialize misc host control in PCI block. */
tp->misc_host_ctrl);
if (pci_latency < 64) {
}
/* If this is a 5700 BX chipset, and we are in PCI-X
* mode, enable register write workaround.
*
* The workaround is to use indirect register accesses
* for all chip writes not to mailbox registers.
*
* In etherboot to simplify things we just always use this work around.
*/
if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
}
/* Back to back register writes can cause problems on the 5701,
* the workaround is to read back all reg writes except those to
* mailbox regs.
* In etherboot we always use indirect register accesses so
* we don't see this.
*/
if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
/* Chip-specific fixup from Broadcom driver */
(!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
}
/* Force the chip into D0. */
/* Etherboot does not ask the tg3 to do checksums */
/* Etherboot does not ask the tg3 to do jumbo frames */
/* Ehterboot does not ask the tg3 to use WakeOnLan. */
/* A few boards don't want Ethernet@WireSpeed phy feature */
}
/* Avoid tagged irq status etherboot does not use irqs */
/* Only 5701 and later support tagged irq status mode.
* Also, 5788 chips cannot use tagged irq status.
*
* However, since etherboot does not use irqs avoid tagged irqs
* status because the interrupt condition is more difficult to
* fully clear in that mode.
*/
/* Since some 5700_AX && 5700_BX have problems with 32BYTE
* coalesce_mode, and the rest work fine anything set.
* Don't enable HOST_CC_MODE_32BYTE in etherboot.
*/
/* Initialize MAC MI mode, polling disabled. */
/* Initialize data/descriptor byte/word swapping. */
/* Clear this out for sanity. */
/* Etherboot does not need to check if the PCIX_TARGET_HWBUG
* is needed. It always uses it.
*/
udelay(50);
/* The TX descriptors will reside in main memory.
*/
/* See which board we are using.
*/
}
/* these are limited to 10/100 only */
}
if (err) {
}
/* 5700 BX chips need to have their TX producer index mailboxes
* written twice to workaround a bug.
* In etherboot we do this unconditionally to simplify things.
*/
/* 5700 chips can get confused if TX buffers straddle the
* 4GB address boundary in some cases.
*
* In etherboot we can ignore the problem as etherboot lives below 4GB.
*/
/* In etherboot wake-on-lan is unconditionally disabled */
return err;
}
{
mac_offset = 0x7c;
else
mac_offset = 0xcc;
/* First try to get it from MAC address mailbox. */
}
/* Next, try NVRAM. */
}
/* Finally just fetch it out of the MAC control regs. */
else {
}
return 0;
}
{
tw32(TG3PCI_CLOCK_CTRL, 0);
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
}
} else {
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
else
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
/* Wheee, some more chip bugs... */
}
}
}
}
return 0;
}
{
tp->carrier_ok = 0;
}
#if SUPPORT_PHY_STR
{
case PHY_ID_BCM5400: return "5400";
case PHY_ID_BCM5401: return "5401";
case PHY_ID_BCM5411: return "5411";
case PHY_ID_BCM5701: return "5701";
case PHY_ID_BCM5703: return "5703";
case PHY_ID_BCM5704: return "5704";
case PHY_ID_BCM8002: return "8002";
case PHY_ID_SERDES: return "serdes";
default: return "unknown";
};
}
#else
#endif
{
if (tp->carrier_ok?
(mac_stat & MAC_STATUS_PCS_SYNCED)) {
}
}
else {
if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
}
}
}
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
{
/*
* writing any value to intr-mbox-0 clears PCI INTA# and
* chip-internal interrupt pending events.
* writing non-zero to intr-mbox-0 additional tells the
* NIC to stop sending us irqs, engaging "in-intr-handler"
* event coalescing.
*/
0x00000001);
/*
* Flush PCI write. This also guarantees that our
* status block has been flushed to host memory.
*/
}
}
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int result;
result = 0;
return 1;
unsigned int len;
result = 1;
}
/* ACK the status ring */
/* Refill RX ring. */
if (result) {
}
}
return result;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
#if 0
{
if (is_end) {
flags |= TXD_FLAG_END;
}
}
#endif
{
static struct eth_frame {
static int frame_idx;
/* send the packet to destination */
int i;
/* Wait until there is a free packet frame */
i = 0;
if (++i > 500) { /* timeout 5s for transmit */
printf("transmit timed out\n");
return;
}
}
if (i != 0) {
printf("#");
}
/* Copy the packet to the our local buffer */
/* Setup the ring buffer entry to transmit */
/* Advance to the next entry */
frame_idx ^= 1;
/* Packets are ready, update Tx producer idx local and on card */
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
{
/* put the card in its initial state */
/* This function serves 3 purposes.
* This disables DMA and interrupts so we don't receive
* unexpected packets or interrupts from the card after
* etherboot has finished.
* This frees resources so etherboot may use
* this driver on another interface
* This allows etherboot to reinitialize the interface
* if something is something goes wrong.
*/
tp->carrier_ok = 0;
}
/**************************************************************************
IRQ - Enable, Disable, or Force interrupts
***************************************************************************/
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
You should omit the last argument struct pci_device * for a non-PCI NIC
***************************************************************************/
{
if (pdev == 0)
return 0;
/* Find power-management capability. */
if (pm_cap == 0) {
printf("Cannot find PowerManagement capability, aborting.\n");
return 0;
}
if (tg3reg_base == -1UL) {
printf("Unuseable bar\n");
return 0;
}
* swapping. DMA data byte swapping is controlled in the GRC_MODE
* setting below.
*/
tp->misc_host_ctrl =
* on descriptor entries, anything which isn't packet data.
*
* The StrongARM chips on the board (one for tx, one for rx)
* are running in big-endian mode.
*/
#if __BYTE_ORDER == __BIG_ENDIAN
#endif
printf("Cannot map device registers, aborting\n");
return 0;
}
if (err) {
printf("Problem fetching invariants of chip, aborting.\n");
goto err_out_iounmap;
}
if (err) {
printf("Could not obtain valid ethernet address, aborting.\n");
goto err_out_iounmap;
}
/* Now that we have fully setup the chip, save away a snapshot
* of the PCI config space. We need to restore this after
* GRC_MISC_CFG core clock resets and some resume events.
*/
printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
if (err) {
goto err_out_disable;
}
/* Wait for a reasonable time for the link to come up */
mdelay(1);
}
if (!tp->carrier_ok){
printf("Valid link not established\n");
goto err_out_disable;
}
return 1;
return 0;
return 0;
}
};
.type = NIC_DRIVER,
.name = "TG3",
.class = 0,
};