/* $Id: tg3.h,v 1.3 2003/02/25 06:02:58 ebiederm Exp $
* tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
*
* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
* Copyright (C) 2001 Jeff Garzik (jgarzik@mandrakesoft.com)
*/
#ifndef _T3_H
#define _T3_H
#include "stdint.h"
typedef unsigned long dma_addr_t;
/* From mii.h */
/* Indicates what features are advertised by the interface. */
/* The following are all involved in forcing a particular link
* mode for the device for setting things. When getting the
* devices settings, these indicate the current mode and whether
* it was foced up into this mode or autonegotiated.
*/
/* The forced speed, 10Mb, 100Mb, gigabit. */
#define SPEED_10 0
/* Duplex, half or full. */
/* Which connector port. */
/* Which tranceiver to use. */
/* Enable or disable autonegotiation. If this is set to enable,
* the forced link modes above are completely ignored.
*/
/* Wake-On-Lan options. */
/* Generic MII registers. */
/* Basic mode control register. */
/* Basic mode status register. */
/* Advertisement control register. */
/* Link partner ability register. */
/* Expansion register for auto-negotiation. */
/* N-way test register. */
/* From tg3.h */
/* Descriptor block info. */
/* First 256 bytes are a mirror of PCI config space. */
/* 0x18 --> 0x2c unused */
/* 0x35 --> 0x3c unused */
/* 0x66 --> 0x68 unused */
(((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
#define DMA_RWCTRL_MIN_DMA_SHIFT 0
/* 0x94 --> 0x98 unused */
/* 0xb0 --> 0x100 unused */
/* 0x100 --> 0x200 unused */
/* Mailbox registers */
/* MAC control registers */
#define ACPI_LENOFF_LEN_SHIFT 0
#define PCS_TEST_PATTERN_SHIFT 0
#define TX_AUTO_NEG_SHIFT 0
#define RX_AUTO_NEG_SHIFT 0
#define TX_LENGTHS_SLOT_TIME_SHIFT 0
/* 0x508 --> 0x520 unused */
/* 0x598 --> 0x600 unused */
/* 0x624 --> 0x800 unused */
/* 0x8bc --> 0xc00 unused */
/* Send data initiator control registers */
/* 0xc14 --> 0xc80 unused */
/* 0xce0 --> 0x1000 unused */
/* Send data completion control registers */
/* 0x1004 --> 0x1400 unused */
/* Send BD ring selector */
/* 0x140c --> 0x1440 */
/* 0x1480 --> 0x1800 unused */
/* Send BD initiator control registers */
/* 0x1848 --> 0x1c00 unused */
/* Send BD completion control registers */
/* 0x1c04 --> 0x2000 unused */
/* Receive list placement control registers */
#define RCVLPC_LOCK_REQ_SHIFT 0
/* 0x2020 --> 0x2100 unused */
/* 0x225c --> 0x2400 unused */
/* Receive Data and Receive BD Initiator Control */
/* 0x240c --> 0x2440 unused */
/* 0x247c --> 0x2480 unused */
/* 0x24c4 --> 0x2800 unused */
/* Receive Data Completion Control */
/* 0x2804 --> 0x2c00 unused */
/* Receive BD Initiator Control Registers */
/* 0x2c20 --> 0x3000 unused */
/* Receive BD Completion Control Registers */
/* 0x3014 --> 0x3400 unused */
/* Receive list selector control registers */
/* 0x3408 --> 0x3800 unused */
/* Mbuf cluster free registers */
/* 0x3808 --> 0x3c00 unused */
/* Host coalescing control registers */
/* 0x3c2c --> 0x3c30 unused */
/* 0x3c4c --> 0x3c50 unused */
/* 0x3c5c --> 0x3c80 unused */
/* 0x3d00 --> 0x4000 unused */
/* Memory arbiter control registers */
/* 0x4010 --> 0x4400 unused */
/* Buffer manager control registers */
/* 0x4458 --> 0x4800 unused */
/* Read DMA control registers */
/* 0x4808 --> 0x4c00 unused */
/* Write DMA control registers */
/* 0x4c08 --> 0x5000 unused */
/* Per-cpu register offsets (arm9) */
/* 0xc --> 0x1c reserved */
/* 0x38 --> 0x44 unused */
/* 0x50 --> 0x200 unused */
/* 0x280 --> 0x400 unused */
/* Mailboxes */
/* 0x5a10 --> 0x5c00 */
/* Flow Through queues */
/* 0x5c04 --> 0x5c10 unused */
/* 0x5d20 --> 0x6000 unused */
/* Message signaled interrupt registers */
/* 0x600c --> 0x6400 unused */
/* DMA completion registers */
/* 0x6404 --> 0x6800 unused */
/* GRC registers */
#define EEPROM_ADDR_ADDR_SHIFT 0
/* 0x684c --> 0x6c00 unused */
/* 0x6c00 --> 0x7000 unused */
/* NVRAM Control registers */
/* 0x7024 --> 0x7400 unused */
/* 0x7400 --> 0x8000 unused */
/* 32K Window into NIC internal memory */
/* Offsets into first 32k of NIC internal memory. */
/* Currently this is fixed. */
/* Tigon3 specific PHY MII registers. */
/* XXX Add this to mii.h */
#ifndef ADVERTISE_PAUSE
#endif
#ifndef ADVERTISE_PAUSE_ASYM
#endif
#ifndef LPA_PAUSE
#endif
#ifndef LPA_PAUSE_ASYM
#endif
/* There are two ways to manage the TX descriptors on the tigon3.
* Either the descriptors are in host DMA'able memory, or they
* exist only in the cards on-chip SRAM. All 16 send bds are under
* the same mode, they may not be configured individually.
*
* The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
*
* To use host memory TX descriptors:
* 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
* Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
* 2) Allocate DMA'able memory.
* 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
* a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
* obtained in step 2
* b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
* c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
* of TX descriptors. Leave flags field clear.
* 4) Access TX descriptors via host memory. The chip
* will refetch into local SRAM as needed when producer
* index mailboxes are updated.
*
* To use on-chip TX descriptors:
* 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
* Make sure GRC_MODE_HOST_SENDBDS is clear.
* 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
* a) Set TG3_BDINFO_HOST_ADDR to zero.
* b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
* c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
* 3) Access TX descriptors directly in on-chip SRAM
* using normal {read,write}l(). (and not using
* pointer dereferencing of ioremap()'d memory like
* the broken Broadcom driver does)
*
* Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
* TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
*/
struct tg3_tx_buffer_desc {
#define TXD_VLAN_TAG_SHIFT 0
};
struct tg3_rx_buffer_desc {
#define RXD_LEN_SHIFT 0
#define RXD_FLAGS_SHIFT 0
#define RXD_TCPCSUM_SHIFT 0
#define RXD_OPAQUE_INDEX_SHIFT 0
};
struct tg3_ext_rx_buffer_desc {
struct {
};
/* We only use this when testing out the DMA engine
* at probe time. This is the internal format of buffer
* descriptors used by the chip at NIC_SRAM_DMA_DESCS.
*/
struct tg3_internal_buffer_desc {
/* XXX FIX THIS */
#if __BYTE_ORDER == __BIG_ENDIAN
#else
#endif
};
struct tg3_hw_status {
#if __BYTE_ORDER == __BIG_ENDIAN
#else
#endif
#if __BYTE_ORDER == __BIG_ENDIAN
#else
#endif
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
#else
#endif
};
typedef struct {
} tg3_stat64_t;
struct tg3_hw_stats {
/* Statistics maintained by Receive MAC. */
/* Statistics maintained by Transmit MAC. */
/* Statistics maintained by Receive List Placement. */
/* Statistics maintained by Send Data Initiator. */
/* Statistics maintained by Host Coalescing. */
};
enum phy_led_mode {
};
#if 0
/* 'mapping' is superfluous as the chip does not write into
* But the cache behavior is better how we are doing it now.
*/
struct ring_info {
};
struct tx_ring_info {
};
#endif
struct tg3_config_info {
};
struct tg3_link_config {
/* Describes what we're trying to get. */
#if 0
#define SPEED_INVALID 0xffff
#define DUPLEX_INVALID 0xff
#define AUTONEG_INVALID 0xff
#endif
/* Describes what we actually have. */
/* When we go in and out of low power mode we need
* to swap with this state.
*/
#if 0
int phy_is_low_power;
#endif
};
struct tg3_bufmgr_config {
};
struct tg3 {
#if 0
/* SMP locking strategy:
*
* lock: Held during all operations except TX packet
* processing.
*
* tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
*
* If you want to shut up all asynchronous processing you must
* acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
* be disabled to take 'lock' but only softirq disabling is
* necessary for acquisition of 'tx_lock'.
*/
#endif
#if 0
#endif
#if 0
struct net_device_stats net_stats;
struct net_device_stats net_stats_prev;
#endif
unsigned long phy_crc_errors;
#if 0
#endif
#if 0
#define TG3_FLAG_HOST_TXDS 0x00000001
#endif
#if 0
struct timer_list timer;
#endif
#if 0
#endif
/* cache h/w values, often passed straight to h/w */
#if 0
#endif
/* PCI block */
#if 0
#endif
int pm_cap;
/* PHY info */
#if 0
struct pci_device *pdev_peer;
#endif
/* This macro assumes the passed PHY ID is already masked
* with PHY_ID_MASK.
*/
#define KNOWN_PHY_ID(X) \
((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
(X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
(X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
(X) == PHY_ID_BCM5705 || \
(X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
unsigned long regs;
#if 0
struct net_device *dev;
#endif
#endif
#if 0
struct ring_info *rx_std_buffers;
struct tg3_rx_buffer_desc *rx_jumbo;
struct ring_info *rx_jumbo_buffers;
#endif
#if 0
#endif
/* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
#if 0
struct tx_ring_info *tx_buffers;
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
int carrier_ok;
};
#endif /* !(_T3_H) */