H A D | intel_pm.c | 1032 * @pixel_size: display pixel size 1049 int pixel_size, 1060 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 1112 int pixel_size = crtc->fb->bits_per_pixel / 8; local 1117 pixel_size, latency->display_sr); 1127 pixel_size, latency->cursor_sr); 1136 pixel_size, latency->display_hpll_disable); 1145 pixel_size, latency->cursor_hpll_disable); 1172 int htotal, hdisplay, clock, pixel_size; local 1186 pixel_size 1046 intel_calculate_wm(unsigned long clock_in_khz, const struct intel_watermark_params *wm, int fifo_size, int pixel_size, unsigned long latency_ns) argument 1256 int hdisplay, htotal, pixel_size, clock; local 1302 int clock, pixel_size; local 1497 int pixel_size = crtc->fb->bits_per_pixel / 8; local 1616 int pixel_size = enabled->fb->bits_per_pixel / 8; local 1751 int hdisplay, htotal, pixel_size, clock; local 2635 haswell_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument 2656 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, uint32_t sprite_width, int pixel_size, const struct intel_watermark_params *display, int display_latency_ns, int *sprite_wm) argument 2688 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, uint32_t sprite_width, int pixel_size, const struct intel_watermark_params *display, int latency_ns, int *sprite_wm) argument 2731 sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument 2854 intel_update_sprite_watermarks(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument [all...] |