/*
*/
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
/*
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* Copyright (c) 2009, 2013, Intel Corporation.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _I915_DRV_H_
#define _I915_DRV_H_
#include "i915_drm.h"
#include "i915_reg.h"
#include "intel_bios.h"
#include "intel_ringbuffer.h"
/* General customization:
*/
enum pipe {
PIPE_A = 0,
};
enum transcoder {
TRANSCODER_A = 0,
};
enum plane {
PLANE_A = 0,
};
enum port {
PORT_A = 0,
};
enum intel_display_power_domain {
};
enum hpd_pin {
HPD_NONE = 0,
};
#define I915_GEM_GPU_DOMAINS \
list_for_each_entry((_intel_encoder), struct intel_encoder, &(dev)->mode_config.encoder_list, base.head) \
struct drm_i915_private;
enum intel_dpll_id {
/* real shared dpll ids must be >= 0 */
};
struct intel_dpll_hw_state {
};
struct intel_shared_dpll {
const char *name;
/* should match the index in the dev_priv->shared_dplls array */
struct intel_shared_dpll *pll);
struct intel_shared_dpll *pll);
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state);
};
/* Used by dp and fdi links */
struct intel_link_m_n {
};
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n);
extern int gpu_dump;
struct intel_ddi_plls {
int spll_refcount;
int wrpll1_refcount;
int wrpll2_refcount;
};
/* Interface history:
*
* 1.1: Original.
* 1.2: Add Power Management
* 1.3: Add vblank support
* 1.4: Fix cmdbuffer path, add heap destroy
* 1.5: Add vblank pipe configuration
* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
* - Support vertical blank on secondary display pipe
*/
#define WATCH_COHERENCY 0
#define WATCH_LISTS 0
#define WATCH_GTT 0
struct drm_i915_gem_phys_object {
int id;
};
struct mem_block {
int start;
int size;
};
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;
struct intel_opregion {
void *vbt;
};
struct intel_overlay;
struct intel_overlay_error_state;
struct drm_i915_master_private {
};
/* 16 fences + sign bit for FENCE_REG_NONE */
struct drm_i915_fence_reg {
int pin_count;
};
struct sdvo_device_mapping {
};
struct intel_display_error_state;
struct drm_i915_error_state {
/* our own tracking of ring head and tail */
struct drm_i915_error_ring {
struct drm_i915_error_object {
int page_count;
struct drm_i915_error_request {
long err_jiffies;
} *requests;
int num_requests;
struct drm_i915_error_buffer {
};
struct intel_crtc_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
struct drm_i915_display_funcs {
/**
* find_dpll() - Find the best values for the PLL
* @limit: limits for the PLL
* @crtc: current CRTC
* @target: target frequency in kHz
* @refclk: reference clock frequency in kHz
* @match_clock: if provided, @best_clock P divider must
* match the P divider from @match_clock
* used for LVDS downclocking
* @best_clock: best PLL values found
*
* Returns true on success, false on failure.
*/
struct dpll *match_clock,
struct dpll *best_clock);
bool enable);
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
struct intel_crtc_config *);
int x, int y,
struct drm_framebuffer *old_fb);
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj);
int x, int y);
/* clock updates for mode set */
/* cursor updates */
};
struct drm_i915_gt_funcs {
};
#define SEP_SEMICOLON ;
struct intel_device_info {
};
enum i915_cache_level {
I915_CACHE_NONE = 0,
};
/* The Graphics Translation Table is the way in which GEN hardware translates a
* Graphics Virtual Address into a Physical Address. In addition to the normal
* collateral associated with any va->pa translations GEN hardware also has a
* portion of the GTT which can be mapped by the CPU and remain both coherent
* and correct (in cases like swizzling). That region is referred to as GMADR in
* the spec.
*/
struct i915_gtt {
/* global gtt ops */
struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
enum i915_cache_level level);
};
struct i915_hw_ppgtt {
unsigned num_pd_entries;
/* pte functions, mirroring the interface of the global gtt. */
unsigned int first_entry,
unsigned int num_entries);
unsigned first_entry, unsigned num_entries,
enum i915_cache_level level);
};
struct i915_ctx_hang_stats {
/* This context had batch pending when hang was declared */
unsigned batch_pending;
/* This context had batch active when hang was declared */
unsigned batch_active;
};
/* This must match up with the value previously used for execbuf2.rsvd1. */
#define DEFAULT_CONTEXT_ID 0
struct i915_hw_context {
int id;
bool is_initialized;
};
enum no_fbc_reason {
};
enum intel_pch {
};
enum intel_sbi_destination {
};
struct intel_fbdev;
struct intel_fbc_work;
struct intel_gmbus {
bool force_bit;
};
typedef struct drm_i915_bridge_dev {
struct i915_suspend_saved_registers {
};
struct batch_info_list {
};
struct intel_gen6_power_mgmt {
/* lock - irqsave spinlock that protectects the work_struct and
* pm_iir. */
/* The below variables an all the rps hw state are protected by
* dev->struct mutext. */
/*
* Must be taken after struct_mutex if nested.
*/
};
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;
struct intel_ilk_power_mgmt {
unsigned long last_time1;
unsigned long chipset_power;
unsigned long gfx_power;
int c_m;
int r_t;
};
/* Power well structure for haswell */
struct i915_power_well {
int count;
int i915_request;
};
struct i915_dri1_state {
unsigned int cpp;
int back_offset;
int front_offset;
int current_page;
int page_flipping;
};
struct intel_l3_parity {
};
struct i915_gem_mm {
/** Memory allocator for GTT stolen memory */
/** Memory allocator for GTT */
/** List of all objects in gtt_space. Used to restore gtt
* mappings on resume */
/**
* List of objects which are not bound to the GTT (thus
* are idle and not used by the GPU) but still have
* (presumably uncached) pages still attached.
*/
/** Usable portion of the GTT for GEM */
int gtt_mtrr;
/** PPGTT used for aliasing the PPGTT with the GTT */
/**
* List of objects currently involved in rendering.
*
* Includes buffers having the contents of their GPU caches
* flushed, not necessarily primitives. last_rendering_seqno
* represents when the rendering involved will be completed.
*
* A reference is held on the buffer while on this list.
*/
/**
* LRU list of objects which are not in the ringbuffer and
* are ready to unbind, but are still in the GTT.
*
* last_rendering_seqno is 0 while an object is in this list.
*
* A reference is not held on the buffer while on this list,
* as merely being GTT-bound shouldn't prevent its being
* freed, and we'll pull it off the list in the free path.
*/
/** LRU list of objects with fence regs on them. */
/**
* We leave the user IRQ off as much as possible,
* but this means that requests will finish and never
* be retired once the system goes idle. Set a timer to
* fire periodically while the ring is running. When it
* fires, go retire requests.
*/
/**
* Are we in a non-interruptible section of code like
* modesetting?
*/
bool interruptible;
/**
* Flag if the X Server, and thus DRM, is not currently in
* control of the device.
*
* This is set between LeaveVT and EnterVT. It needs to be
* replaced with a semaphore. It also needs to be
* transitioned away from for kernel modesetting.
*/
int suspended;
/** Bit 6 swizzling required for X tiling */
/** Bit 6 swizzling required for Y tiling */
/* storage for physical objects */
/* accounting, useful for userland debugging */
};
struct drm_i915_error_state_buf {
unsigned bytes;
unsigned size;
int err;
};
struct i915_gpu_error {
/* For hangcheck timer */
/* For reset and error_state handling. */
/* Protected by the above dev->gpu_error.lock. */
unsigned long last_reset;
/**
* State variable and reset counter controlling the reset flow
*
* Upper bits are for the reset counter. This counter is used by the
* wait_seqno code to race-free noticed that a reset event happened and
* that it needs to restart the entire ioctl (since most likely the
* seqno it waited for won't ever signal anytime soon).
*
* This is important for lock-free wait paths, where no contended lock
* naturally enforces the correct ordering between the bail-out of the
* waiter and the gpu reset work code.
*
* Lowest bit controls the reset state machine: Set means a reset is in
* progress. This state will (presuming we don't have any bugs) decay
* into either unset (successful reset) or the special WEDGED value (hw
* terminally sour). All waiters on the reset_queue will be woken when
* that happens.
*/
/**
*
* Note that the code relies on
* I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
* being true.
*/
/**
* Waitqueue to signal when the reset has completed. Used by clients
* that wait for dev_priv->mm.wedged to settle.
*/
/* For gpu hang simulation. */
unsigned int stop_rings;
};
enum modeset_restore {
};
struct intel_vbt_data {
/* Feature bits */
int lvds_ssc_freq;
/* eDP */
int edp_rate;
int edp_lanes;
int edp_preemphasis;
int edp_vswing;
bool edp_initialized;
bool edp_support;
int edp_bpp;
int crt_ddc_pin;
int child_dev_num;
};
typedef struct drm_i915_private {
/** gt_fifo_count and the subsequent register write are synchronized
* with dev->struct_mutex. */
unsigned gt_fifo_count;
/** forcewake_count is protected by gt_lock */
unsigned forcewake_count;
/** gt_lock is also taken in irq contexts. */
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
* controller on different i2c buses. */
/**
* Base address of the gmbus and gpio block.
*/
/* protects the irq masks */
/* DPIO indirect register protection */
/** Cached value of IMR to avoid reads in updating the bitfield */
struct {
unsigned long hpd_last_jiffies;
int hpd_cnt;
enum {
HPD_ENABLED = 0,
} hpd_mark;
int num_plane;
unsigned long cfb_size;
unsigned int cfb_fb;
int cfb_y;
/* overlay */
unsigned int sprite_scaling_enabled;
/* backlight */
struct {
int level;
bool enabled;
} backlight;
/* LVDS info */
bool no_aux_handshake;
/* Display functions */
/* PCH chipset type */
unsigned short pch_id;
unsigned long quirks;
bool vt_holding;
bool isX;
bool gfx_state_saved;
/* Register state */
/* Kernel Modesetting */
int num_shared_dpll;
/* Reclocking support */
bool render_reclock_avail;
bool lvds_downclock_avail;
/* indicates the reduced downclock for LVDS*/
int lvds_downclock;
bool mchbar_need_disable;
/* gen6+ rps state */
* mchdev_lock in intel_pm.c */
/* Haswell power well */
int gpu_hang;
/* list of fbdev register on this device */
bool hw_contexts_disabled;
/* Old dri1 support infrastructure, beware the dragons ya fools entering
* here! */
/* Iterate over initialised rings */
enum hdmi_force_audio {
};
struct drm_i915_gem_object_ops {
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
* of pages before to binding them into the GTT, and put_pages() is
* called after we no longer need them. As we expect there to be
* associated cost with migrating pages between the backing storage
* and making them available for the GPU (e.g. clflush), we may hold
* onto the pages after they are no longer referenced by the GPU
* in case they may be used again shortly (for example migrating the
* pages to a different memory domain within the GTT). put_pages()
* will therefore most likely be called when the object itself is
* being released or under memory pressure (where we attempt to
* reap pages for the shrinker).
*/
};
struct drm_i915_gem_object {
/** Current space allocated to this object in the GTT, if any. */
/** Stolen memory for this object, instead of being backed by shmem. */
/** This object's place on eviction list */
/**
* This is set if the object is on the active or flushing lists
* (has pending rendering), and is not set if it's on inactive (ready
* to be unbound).
*/
unsigned int active;
/**
* This is set if the object has been written to since last bound
* to the GTT
*/
unsigned int dirty;
/**
* Fence register bits (if any) for this object. Will be set
* as needed when mapped into the GTT.
* Protected by dev->struct_mutex.
*/
signed int fence_reg;
/**
* Advice: are the backing pages purgeable?
*/
unsigned int madv;
/**
* Current tiling mode for the object.
*/
/**
* Whether the tiling parameters for the currently associated fence
* register have changed. Note that for the purposes of tracking
* tiling changes we also treat the unfenced register, the register
* slot that the object occupies whilst it executes a fenced
* command (such as BLT on gen2/3), as a "fence".
*/
/** How many users have pinned this object in GTT space. The following
* (via user_pin_count), execbuffer (objects are not allowed multiple
* times for the same batchbuffer), and the framebuffer code. When
* switching/pageflipping, the framebuffer code has at most two buffers
* pinned per crtc.
*
* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
* bits with absolutely no headroom. So use 4 bits. */
unsigned int pin_count;
/**
* Is the object at the current location in the gtt mappable and
* fenceable? Used to avoid costly recalculations.
*/
unsigned int map_and_fenceable;
int agp_mem;
/**
* Whether the current gtt mapping needs to be mappable (and isn't just
* mappable by accident). Track pin and fault separate for a more
* accurate mappable working set.
*/
unsigned int fault_mappable;
unsigned int pin_mappable;
/*
* Is the GPU currently using a fence to access this buffer,
*/
unsigned int pending_fenced_gpu_access;
unsigned int fenced_gpu_access;
unsigned int cache_level;
unsigned int has_aliasing_ppgtt_mapping;
unsigned int has_global_gtt_mapping;
unsigned int has_dma_mapping;
int pages_pin_count;
/**
* DMAR support
*/
int num_sg;
/**
* Used for performing relocations during execbuffer insertion.
*/
unsigned long exec_handle;
/**
* Current offset of the object in GTT space.
*
* This is the same as gtt_space->start
*/
/**
* Fake offset for use by mmap(2)
*/
/** Breadcrumb of last rendering to the buffer. */
/** Breadcrumb of last fenced GPU access to the buffer. */
/** Current tiling mode for the object. */
/** Record of address bit 17 of each page at last unbind. */
unsigned long *bit_17;
/** User space pin count and filp owning the pin */
/** for phy allocated objects */
/** OSOL: for cursor objects */
};
/**
* Request queue structure.
*
* The request queue allows us to note sequence numbers that have been emitted
* and may be associated with active buffers to be retired.
*
* By keeping this list, we can avoid having to do questionable
* sequence-number comparisons on buffer last_rendering_seqnos, and associate
* an emission time with seqnos for tracking how far ahead of the GPU we are.
*/
struct drm_i915_gem_request {
/** On Which ring this request was generated */
/** GEM sequence number associated with this request. */
/** Position in the ringbuffer of the start of the request */
/** Postion in the ringbuffer of the end of the request */
/** Context related to this request */
/** Batch buffer related to this request if any */
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
/** global list entry for this request */
/** file_priv list entry for this request */
};
struct drm_i915_file_private {
struct {
} mm;
/** 1 open, 0 close*/
int status;
};
#if defined(__sun)
/* These definitions conflict with those in x86_archext.h */
#endif
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
/* dsparb controlled by hw only */
/**
* RC6 is a special power stage which allows the GPU to enter an very
* low-voltage mode when idle, using down to 0V while at this stage. This
* stage is entered automatically when the GPU is idle when RC6 support is
* enabled, and as soon as new workload arises GPU wakes up automatically as well.
*
* There are different RC6 modes available in Intel GPU, which differentiate
* among each other with the latency required to enter and leave RC6 and
* voltage consumed by the GPU in different states.
*
* The combination of the following flags define which states GPU is allowed
* to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
* RC6pp is deepest RC6. Their support by hardware varies according to the
* GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
* which brings the most power savings; deeper states save more power, but
* require higher latency to switch to and wake up.
*/
extern struct drm_ioctl_desc i915_ioctls[];
extern int i915_max_ioctl;
extern unsigned int i915_fbpercrtc;
extern int i915_panel_ignore_lid;
extern unsigned int i915_powersave;
extern int i915_semaphores;
extern unsigned int i915_lvds_downclock;
extern int i915_lvds_channel_mode;
extern int i915_panel_use_ssc;
extern int i915_vbt_sdvo_panel_type;
extern int i915_enable_rc6;
extern int i915_enable_fbc;
extern bool i915_enable_hangcheck;
extern bool i915_try_reset;
extern int i915_enable_ppgtt;
extern int i915_disable_power_well;
extern int i915_enable_ips;
/* i915_dma.c */
extern int i915_driver_unload(struct drm_device *);
#ifdef CONFIG_COMPAT
unsigned long arg);
#endif
struct drm_clip_rect *box,
extern int i915_bridge_dev_read_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 *val);
extern int i915_bridge_dev_write_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 val);
extern void gpu_top_handler(void *data);
/* i915_irq.c */
void i915_hangcheck_elapsed(void* data);
void
void
#ifdef CONFIG_DEBUG_FS
#else
#define i915_destroy_error_state(x)
#endif
/* i915_gem.c */
const struct drm_i915_gem_object_ops *ops);
bool map_and_fenceable,
bool nonblocking);
{
obj->pages_pin_count++;
}
{
obj->pages_pin_count--;
}
struct intel_ring_buffer *to);
struct intel_ring_buffer *ring);
struct drm_device *dev,
struct drm_mode_create_dumb *args);
/**
* Returns true if seq1 is later than seq2.
*/
static inline bool
{
}
static inline bool
{
return true;
} else
return false;
}
static inline void
{
}
}
bool interruptible);
{
}
{
}
struct drm_i915_gem_object *batch_obj,
bool write);
int
int
struct intel_ring_buffer *pipelined);
struct drm_i915_gem_object *obj,
int id,
int align);
struct drm_i915_gem_object *obj);
int tiling_mode, bool fenced);
enum i915_cache_level cache_level);
/* i915_gem_context.c */
struct i915_ctx_hang_stats *
/* i915_gem_gtt.c */
struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
struct drm_i915_gem_object *obj);
enum i915_cache_level cache_level);
unsigned long mappable_end, unsigned long end);
/* i915_gem_evict.c */
unsigned alignment,
unsigned cache_level,
bool mappable,
bool nonblock);
/* i915_gem_stolen.c */
struct drm_i915_gem_object *
struct drm_i915_gem_object *
/* i915_gem_tiling.c */
{
}
/* i915_gem_debug.c */
#if WATCH_LISTS
#else
#endif
int handle);
/* i915_suspend.c */
/* i915_ums.c */
/* intel_i2c.c */
{
}
extern struct i2c_adapter *intel_gmbus_get_adapter(
{
}
/* modesetting */
bool force_restore);
/* overlay */
#ifdef CONFIG_DEBUG_FS
extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
extern void intel_display_print_error_state(struct seq_file *m,
struct drm_device *dev,
struct intel_display_error_state *error);
#endif
/* On SNB platform, before reading ring registers forcewake bit
* must be set to prevent GT core from power down and stale values being
* returned.
*/
/* intel_sideband.c */
enum intel_sbi_destination destination);
enum intel_sbi_destination destination);
#define __i915_read(x) \
__i915_read(8)
__i915_read(16)
__i915_read(32)
__i915_read(64)
#define __i915_write(x) \
u ## x val);
__i915_write(8)
__i915_write(16)
__i915_write(32)
__i915_write(64)
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
{
if (HAS_PCH_SPLIT(dev))
return CPU_VGACNTRL;
else if (IS_VALLEYVIEW(dev))
return VLV_VGACNTRL;
else
return VGACNTRL;
}
#endif /* _I915_DRV_H_ */