/*
*/
/*
* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
* Copyright (c) 2007-2008, 2013, Intel Corporation
* Jesse Barnes <jesse.barnes@intel.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__
#include "i915_drv.h"
#include "i915_drm.h"
#include "drm_crtc.h"
#include "drm_sun_i2c.h" /* OSOL_i915 */
#include "drm_crtc_helper.h"
#include "drm_fb_helper.h"
#include "drm_dp_helper.h"
#define MSLEEP(x) do { \
if (in_dbg_master()) \
mdelay(x); \
else \
msleep(x); \
} while(0)
/*
* Display related stuff
*/
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
/* maximum connectors per crtcs in the mode set */
/* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
#define INTEL_OUTPUT_UNUSED 0
#define INTEL_DVO_CHIP_NONE 0
struct intel_framebuffer {
};
struct intel_fbdev {
};
struct intel_encoder {
/*
* The new crtc this encoder will be driven from. Only differs from
* base->crtc while a modeset is in progress.
*/
int type;
int type_size;
/*
* Intel hw has only one MUX where encoders could be clone, hence a
* simple flag is enough to compute the possible_clones mask.
*/
bool cloneable;
bool connectors_active;
struct intel_crtc_config *);
/* Read out the current hw state of this connector, returning true if
* the encoder is active. If the encoder is enabled it also set the pipe
* it is connected to in the pipe parameter. */
/* Reconstructs the equivalent mode flags for the current hardware
* state. This must be called _after_ display->get_pipe_config has
* pre-filled the pipe config. Note that intel_encoder->base.crtc must
* be set correctly before calling this function. */
struct intel_crtc_config *pipe_config);
int crtc_mask;
};
struct intel_panel {
int fitting_mode;
};
struct intel_connector {
/*
* The fixed encoder this connector is connected to.
*/
/*
* The new encoder this connector will be driven. Only differs from
* encoder while a modeset is in progress.
*/
/* Reads out the current hw, returning true if the connector is enabled
* and active (i.e. dpms ON state). */
/* Panel info for eDP and LVDS */
/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
/* since POLL and HPD connectors may use the same HPD line keep the native
state of connector->polled in case hotplug storm detection changes it */
};
typedef struct dpll {
/* given values */
int n;
/* derived values */
int dot;
int vco;
int m;
int p;
struct intel_crtc_config {
/**
* quirks - bitfield with hw state readout quirks
*
* For various reasons the hw state readout code might not be able to
* completely faithfully read out the current state. These cases are
* tracked with quirk flags so that fastboot and state checker can act
* accordingly.
*/
unsigned long quirks;
/* This flag must be set by the encoder's compute_config callback if it
* changes the crtc timings in the mode to prevent the crtc fixup from
* overwriting them. Currently only lvds needs that. */
bool timings_set;
* between pch encoders and cpu encoders. */
bool has_pch_encoder;
/* CPU Transcoder for the pipe. Currently this can only differ from the
* pipe on Haswell (where we have a special eDP transcoder). */
/*
* range fed into the crtcs.
*/
bool limited_color_range;
/* DP has a bunch of special case unfortunately, so mark the pipe
* accordingly. */
bool has_dp_encoder;
/*
* Enable dithering, used when the selected pipe bpp doesn't match the
* plane bpp.
*/
bool dither;
/* Controls for the clock computation, to override various stages. */
bool clock_set;
/* SDVO TV has a bunch of special case. To make multifunction encoders
* work correctly, we need to track this at runtime.*/
bool sdvo_tv_clock;
/*
* crtc bandwidth limit, don't increase pipe bpp or clock if not really
* required. This is set in the 2nd loop of calling encoder's
* ->compute_config if the first pick doesn't work out.
*/
bool bw_constrained;
/* Settings for the intel dpll used on pretty much everything but
* haswell. */
/* Selected dpll when shared or DPLL_ID_PRIVATE. */
/* Actual register state of the dpll, for shared dpll cross-checking. */
int pipe_bpp;
/*
* Frequence the dpll for the port should run at. Differs from the
* adjusted dotclock e.g. for DP or 12bpc hdmi mode.
*/
int port_clock;
/* Used by SDVO (and if we ever fix it, HDMI). */
unsigned pixel_multiplier;
/* Panel fitter controls for gen2-gen4 + VLV */
struct {
} gmch_pfit;
/* Panel fitter placement and size for Ironlake+ */
struct {
} pch_pfit;
/* FDI configuration, only valid if has_pch_encoder is set. */
int fdi_lanes;
bool ips_enabled;
};
struct intel_crtc {
/*
* Whether the crtc and the connected output pipeline is active. Implies
* that crtc->enabled is set, i.e. the current mode configuration has
* some outputs connected to this crtc.
*/
bool active;
bool eld_vld;
bool lowfreq_avail;
/* Display surface base address adjustement for pageflips. Note that on
* gen4+ this only adjusts up to a tile, offsets within a tile are
* handled in the hw itself (with the TILEOFF register). */
unsigned long dspaddr_offset;
bool cursor_visible;
/* reset counter value when the last flip was submitted */
unsigned int reset_counter;
/* Access to these should be protected by dev_priv->irq_lock. */
};
struct intel_plane {
int plane;
bool can_scale;
int max_downscale;
* as the other pieces of the struct may not reflect the values we want
* for the watermark calculations. Currently only Haswell uses this.
*/
struct {
bool enable;
} wm;
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
int x, int y,
struct drm_intel_sprite_colorkey *key);
struct drm_intel_sprite_colorkey *key);
};
struct intel_watermark_params {
unsigned long fifo_size;
unsigned long max_wm;
unsigned long default_wm;
unsigned long guard_size;
unsigned long cacheline_size;
};
struct cxsr_latency {
int is_desktop;
int is_ddr3;
unsigned long fsb_freq;
unsigned long mem_freq;
unsigned long display_sr;
unsigned long display_hpll_disable;
unsigned long cursor_sr;
unsigned long cursor_hpll_disable;
};
#define DIP_AVI_PR_1 0
#define DIP_SPD_UNKNOWN 0
struct dip_infoframe {
union {
struct {
/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
/* PB2 - C 7:6, M 5:4, R 3:0 */
/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
/* PB4 - VIC 6:0 */
/* PB5 - PR 3:0 */
/* PB6 to PB13 */
} avi;
struct {
} spd;
} __attribute__((packed));
struct intel_hdmi {
int ddc_bus;
bool color_range_auto;
bool has_hdmi_sink;
bool has_audio;
struct dip_infoframe *frame);
struct drm_display_mode *adjusted_mode);
};
struct intel_dp {
bool has_audio;
bool color_range_auto;
int panel_power_up_delay;
int backlight_on_delay;
int backlight_off_delay;
bool want_panel_vdd;
};
struct intel_digital_port {
};
static inline int
{
case PORT_B:
return (0);
case PORT_C:
return (1);
default:
BUG();
}
return (0);
}
static inline struct drm_crtc *
{
}
static inline struct drm_crtc *
{
}
struct intel_unpin_work {
#define INTEL_FLIP_INACTIVE 0
bool enable_stall_check;
};
struct intel_fbc_work {
unsigned long interval;
};
struct intel_connector *intel_connector);
struct intel_crtc_config *pipe_config);
bool is_sdvob);
struct intel_ring_buffer *ring);
struct intel_connector *intel_connector);
struct intel_crtc_config *pipe_config);
/* intel_panel.c */
struct drm_display_mode *fixed_mode);
struct drm_display_mode *adjusted_mode);
struct intel_crtc_config *pipe_config,
int fitting_mode);
struct intel_crtc_config *pipe_config,
int fitting_mode);
struct intel_set_config {
bool fb_changed;
bool mode_changed;
};
int x, int y, struct drm_framebuffer *old_fb);
{
}
static inline struct intel_digital_port *
{
}
{
}
static inline struct intel_digital_port *
{
}
static inline struct intel_digital_port *
{
}
struct intel_digital_port *port);
struct intel_encoder *encoder);
extern enum transcoder
struct intel_load_detect_pipe {
bool load_detect_temp;
int dpms_mode;
};
struct drm_display_mode *mode,
struct intel_load_detect_pipe *old);
struct intel_load_detect_pipe *old);
extern void intelfb_restore(void);
struct drm_i915_gem_object *obj,
struct intel_ring_buffer *pipelined);
struct intel_framebuffer *ifb,
struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_i915_gem_object *obj);
extern int intel_overlay_put_image(DRM_IOCTL_ARGS);
extern int intel_overlay_attrs(DRM_IOCTL_ARGS);
bool state);
struct drm_display_mode *mode);
/* For use by IVB LP watermark workaround in intel_sprite.c */
int pixel_size, bool enable);
extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
unsigned int tiling_mode,
unsigned int bpp,
unsigned int pitch);
extern int intel_sprite_set_colorkey(DRM_IOCTL_ARGS);
extern int intel_sprite_get_colorkey(DRM_IOCTL_ARGS);
/* Power-related functions, located in intel_pm.c */
/* FBC */
/* IPS */
extern void intel_gpu_ips_teardown(void);
/* Power well */
enum intel_display_power_domain domain);
enum transcoder cpu_transcoder);
extern bool
bool enable);
enum transcoder pch_transcoder,
bool enable);
#endif /* __INTEL_DRV_H__ */