Searched refs:regs (Results 1 - 25 of 252) sorted by relevance

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/illumos-gate/usr/src/lib/libdtrace/i386/
H A DMakefile31 DLIBSRCS = regs.d
40 CLEANFILES += regs.sed regs.d
46 ../$(MACH)/regs.d: regs.sed regs.d.in
47 sed -f regs.sed < regs.d.in > $@
/illumos-gate/usr/src/cmd/mdb/sparc/kmdb/
H A Dkmdb_kdi_isadep.h38 struct regs;
42 extern void kmdb_kdi_kernpanic(struct regs *, uint_t);
/illumos-gate/usr/src/cmd/mdb/intel/mdb/
H A Dkvm_amd64dep.c161 kt_regs_to_kregs(struct regs *regs, mdb_tgt_gregset_t *gregs) argument
163 gregs->kregs[KREG_SAVFP] = regs->r_savfp;
164 gregs->kregs[KREG_SAVPC] = regs->r_savpc;
165 gregs->kregs[KREG_RDI] = regs->r_rdi;
166 gregs->kregs[KREG_RSI] = regs->r_rsi;
167 gregs->kregs[KREG_RDX] = regs->r_rdx;
168 gregs->kregs[KREG_RCX] = regs->r_rcx;
169 gregs->kregs[KREG_R8] = regs->r_r8;
170 gregs->kregs[KREG_R9] = regs
198 struct regs regs; local
[all...]
H A Dkvm_ia32dep.c161 kt_regs_to_kregs(struct regs *regs, mdb_tgt_gregset_t *gregs) argument
163 gregs->kregs[KREG_SAVFP] = regs->r_savfp;
164 gregs->kregs[KREG_SAVPC] = regs->r_savpc;
165 gregs->kregs[KREG_EAX] = regs->r_eax;
166 gregs->kregs[KREG_EBX] = regs->r_ebx;
167 gregs->kregs[KREG_ECX] = regs->r_ecx;
168 gregs->kregs[KREG_EDX] = regs->r_edx;
169 gregs->kregs[KREG_ESI] = regs->r_esi;
170 gregs->kregs[KREG_EDI] = regs
192 struct regs regs; local
[all...]
H A Dkvm_isadep.c133 mdb_tgt_gregset_t regs; local
156 if (kt_kvmregs(t, cpuid, &regs) != 0) {
157 mdb_warn("failed to get regs for cpu %d\n", cpuid);
162 * Tell the stack walker that we have regs.
165 addr = regs.kregs[KREG_FP];
178 mdb_tgt_gregset_t regs; local
203 if (kt_kvmregs(t, cpuid, &regs) != 0) {
204 mdb_warn("failed to get regs for cpu %d\n", cpuid);
208 return (kt_regs((uintptr_t)&regs, flags, argc, argv));
/illumos-gate/usr/src/uts/sun4/sys/
H A Dfpras.h87 struct regs;
88 extern int fpras_chktrap(struct regs *);
/illumos-gate/usr/src/uts/common/io/rtw/
H A Drtwphyio.c52 rtw_bbp_read(struct rtw_regs *regs, uint_t addr) argument
54 RTW_WRITE(regs, RTW_BB,
57 RTW_WBR(regs, RTW_BB, RTW_BB);
58 return (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK));
62 rtw_bbp_write(struct rtw_regs *regs, uint_t addr, uint_t val) argument
81 RTW_RBW(regs, RTW_BB, RTW_BB);
82 RTW_WRITE(regs, RTW_BB, wrbbp);
83 RTW_SYNC(regs, RTW_BB, RTW_BB);
84 RTW_WRITE(regs, RTW_BB, rdbbp);
85 RTW_SYNC(regs, RTW_B
104 rtw_rf_hostbangbits(struct rtw_regs *regs, uint32_t bits, int lo_to_hi, uint_t nbits) argument
159 rtw_rf_macbangbits(struct rtw_regs *regs, uint32_t reg) argument
236 rtw_rf_hostwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, uint_t addr, uint32_t val) argument
298 rtw_rf_macwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, uint_t addr, uint32_t val) argument
[all...]
H A Drtw.c252 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) argument
257 dvname, reg, RTW_READ(regs, reg))
262 dvname, reg, RTW_READ16(regs, reg))
267 dvname, reg, RTW_READ8(regs, reg))
271 PRINTREG32(regs, RTW_IDR0);
272 PRINTREG32(regs, RTW_IDR1);
273 PRINTREG32(regs, RTW_MAR0);
274 PRINTREG32(regs, RTW_MAR1);
275 PRINTREG32(regs, RTW_TSFTRL);
276 PRINTREG32(regs, RTW_TSFTR
377 rtw_config0123_enable(struct rtw_regs *regs, int enable) argument
396 rtw_anaparm_enable(struct rtw_regs *regs, int enable) argument
417 struct rtw_regs *regs = &rsc->sc_regs; local
429 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess) argument
479 rtw_set_access(struct rtw_regs *regs, enum rtw_access access) argument
493 struct rtw_regs *regs = &rsc->sc_regs; local
511 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname) argument
536 rtw_chip_reset(struct rtw_regs *regs, const char *dvname) argument
543 rtw_disable_interrupts(struct rtw_regs *regs) argument
553 struct rtw_regs *regs = &rsc->sc_regs; local
566 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname) argument
606 rtw_set_mode(struct rtw_regs *regs, int mode) argument
618 rtw_dma_start(struct rtw_regs *regs, int priority) argument
641 rtw_beacon_tx_disable(struct rtw_regs *regs) argument
656 struct rtw_regs *regs = &rsc->sc_regs; local
790 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr, const char *dvname) argument
883 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, const char *dvname) argument
975 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale, const char *dvname) argument
997 rtw_identify_sta(struct rtw_regs *regs, uint8_t *addr, const char *dvname) argument
1053 rtw_idle(struct rtw_regs *regs) argument
1070 struct rtw_regs *regs = &rsc->sc_regs; local
1310 struct rtw_regs *regs = &rsc->sc_regs; local
1421 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, int before_rf, int digphy) argument
1463 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, int before_rf, int digphy) argument
1500 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power, int before_rf, int digphy) argument
1545 struct rtw_regs *regs = &rsc->sc_regs; local
1665 struct rtw_regs *regs = &rsc->sc_regs; local
1705 rtw_transmit_config(struct rtw_regs *regs) argument
1730 struct rtw_regs *regs; local
1883 rtw_check_phydelay(struct rtw_regs *regs, uint32_t rcr0) argument
2347 struct rtw_regs *regs = &rsc->sc_regs; local
2787 struct rtw_regs *regs = &rsc->sc_regs; local
2850 struct rtw_regs *regs = &rsc->sc_regs; local
2883 struct rtw_regs *regs; local
2967 struct rtw_regs *regs = &rsc->sc_regs; local
2985 struct rtw_regs *regs = &rsc->sc_regs; local
3004 struct rtw_regs *regs = &rsc->sc_regs; local
[all...]
/illumos-gate/usr/src/uts/intel/amd64/sys/
H A Dprivmregs.h54 struct regs pm_gregs;
/illumos-gate/usr/src/uts/intel/ia32/sys/
H A Dprivmregs.h54 struct regs pm_gregs;
/illumos-gate/usr/src/boot/sys/boot/fdt/dts/arm/
H A Darmada-388.dtsi57 internal-regs {
H A Darmada-385.dtsi75 internal-regs {
/illumos-gate/usr/src/uts/sun/io/audio/drv/audiocs/
H A Daudio_4231_eb2dma.c122 audio_dev_warn(state->cs_adev, "failed mapping codec regs");
130 audio_dev_warn(state->cs_adev, "failed mapping play regs");
140 audio_dev_warn(state->cs_adev, "failed mapping rec regs");
252 cs4231_eb2regs_t *regs = eng->ce_eb2regs; local
269 OR_SET_WORD(handle, &regs->eb2csr, EB2_RESET);
272 csr = ddi_get32(handle, &regs->eb2csr);
275 csr = ddi_get32(handle, &regs->eb2csr);
284 AND_SET_WORD(handle, &regs->eb2csr, ~(EB2_RESET|EB2_EN_DMA));
287 OR_SET_WORD(handle, &regs->eb2csr, reset);
297 OR_SET_WORD(handle, &regs
323 cs4231_eb2regs_t *regs = eng->ce_eb2regs; local
391 cs4231_eb2regs_t *regs = eng->ce_eb2regs; local
428 cs4231_eb2regs_t *regs = eng->ce_eb2regs; local
[all...]
/illumos-gate/usr/src/uts/sparc/sys/
H A Dsimulate.h144 extern int simulate_unimp(struct regs *, caddr_t *);
145 extern int simulate_lddstd(struct regs *, caddr_t *);
146 extern int simulate_rdtick(struct regs *);
147 extern int do_unaligned(struct regs *, caddr_t *);
148 extern int calc_memaddr(struct regs *, caddr_t *);
149 extern int is_atomic(struct regs *);
150 extern int instr_size(struct regs *, caddr_t *, enum seg_rw);
151 extern int getreg(struct regs *, uint_t, uint64_t *, caddr_t *);
152 extern int putreg(uint64_t *, struct regs *, uint_t, caddr_t *);
H A Dkdi_machimpl.h44 struct regs;
76 void (*mkdi_kernpanic)(struct regs *, uint_t);
/illumos-gate/usr/src/uts/i86pc/os/
H A Dpci_cfgspace.c252 struct bop_regs regs; local
256 bzero(&regs, sizeof (regs));
257 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
259 BOP_DOINT(bootops, 0x1a, &regs);
260 carryflag = regs.eflags & PS_C;
261 ax = regs.eax.word.ax;
262 dx = regs.edx.word.dx;
276 pci_bios_vers = regs.ebx.word.bx;
277 pci_bios_maxbus = (regs
[all...]
H A Dpci_bios.c70 struct bop_regs regs; local
93 bzero(&regs, sizeof (regs));
94 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_GET_IRQ_ROUTING;
96 regs.ds = 0xf000;
97 regs.es = FP_SEG((uint_t)(uintptr_t)hdrp);
98 regs.edi.word.di = FP_OFF((uint_t)(uintptr_t)hdrp);
100 BOP_DOINT(bootops, 0x1a, &regs);
105 if ((regs.eflags & PS_C) != 0) {
/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcie_nvidia.c222 pci_regspec_t regs[2] = {{0}}; local
228 regs[0].pci_phys_hi = devloc;
233 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE;
234 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B |
236 assigned[0].pci_phys_low = regs[0].pci_phys_low =
242 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE;
243 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B |
245 assigned[1].pci_phys_low = regs[1].pci_phys_low =
249 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int));
/illumos-gate/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_vgatext.c69 struct vgaregmap regs; member in struct:vgatext_softc
421 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE,
422 &dev_attr, &softc->regs.handle);
425 softc->regs.mapped = B_TRUE;
437 if (ddi_get8(softc->regs.handle,
438 softc->regs.addr + VGA_MISC_R) & VGA_MISC_IOA_SEL)
504 if (softc->regs.mapped)
505 ddi_regs_map_free(&softc->regs.handle);
1073 vga_set_crtc(&softc->regs, VGA_CRTC_CLAH, addr >> 8);
1074 vga_set_crtc(&softc->regs, VGA_CRTC_CLA
[all...]
/illumos-gate/usr/src/uts/sparc/v7/sys/
H A Dprivregs.h55 struct regs { struct
60 long r_g1; /* user global regs */
/illumos-gate/usr/src/uts/common/sys/
H A Dpanic.h131 struct regs;
149 extern struct regs *panic_reg;
155 extern void panic_saveregs(panic_data_t *, struct regs *);
/illumos-gate/usr/src/uts/sparc/sys/fpu/
H A Dfpusystm.h41 struct regs;
54 extern void fp_disabled(struct regs *);
58 extern void fp_runq(struct regs *);
/illumos-gate/usr/src/cmd/sgs/librtld_db/demo/
H A DMakefile26 i386/regs.c \
30 amd64/regs.c \
33 sparc/regs.c \
37 sparcv9/regs.c \
67 tests/test-sparc-regs \
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_fm.c56 px_err_pcie_t *regs);
59 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs);
586 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs, argument
600 if (regs->primary_ue & PCIE_AER_UCE_UR)
602 if (regs->primary_ue & PCIE_AER_UCE_CA)
604 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC))
607 if (!regs->primary_ue)
610 adv_reg->pcie_ce_status = regs->ce_reg;
611 adv_reg->pcie_ue_status = regs->ue_reg | regs
649 px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs) argument
666 px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) argument
[all...]
/illumos-gate/usr/src/uts/intel/io/vgatext/
H A Dvgatext.c143 struct vgaregmap regs; member in struct:vgatext_softc
539 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE,
540 &dev_attr, &softc->regs.handle);
543 softc->regs.mapped = B_TRUE;
555 if (ddi_get8(softc->regs.handle,
556 softc->regs.addr + VGA_MISC_R) & VGA_MISC_IOA_SEL)
634 if (softc->regs.mapped)
635 ddi_regs_map_free(&softc->regs.handle);
1199 vga_set_crtc(&softc->regs, VGA_CRTC_CLAH, addr >> 8);
1200 vga_set_crtc(&softc->regs, VGA_CRTC_CLA
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