c88420b3bc75201aa71e3c807fd31e66073a089fdmick * CDDL HEADER START
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * The contents of this file are subject to the terms of the
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * Common Development and Distribution License (the "License").
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * You may not use this file except in compliance with the License.
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * See the License for the specific language governing permissions
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c88420b3bc75201aa71e3c807fd31e66073a089fdmick * When distributing Covered Code, include this CDDL HEADER in each
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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c88420b3bc75201aa71e3c807fd31e66073a089fdmick * information: Portions Copyright [yyyy] [name of copyright owner]
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * CDDL HEADER END
8d7fafffed373567f52062b634e61fd50858b8d9Zhi-Jun Robin Fu * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * PCI configuration space access routines
843e19887f64dde75055cf8842fc4db2171eff45johnlev#if defined(__xpv)
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * These two variables can be used to force a configuration mechanism or
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * to force which function is used to probe for the presence of the PCI bus.
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * No valid mcfg_mem_base by default, and accessing pci config space
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * in mem-mapped way is disabled.
8d7fafffed373567f52062b634e61fd50858b8d9Zhi-Jun Robin Fu * Maximum offset in config space when not using MMIO
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * These function pointers lead to the actual implementation routines
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * for configuration space access. Normally they lead to either the
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * pci_mech1_* or pci_mech2_* routines, but they can also lead to
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * routines that work around chipset bugs.
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * These functions are accessing pci config space via I/O way.
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * which also provide accessing pci config space via mem-mapped way.
c88420b3bc75201aa71e3c807fd31e66073a089fdmickuint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickuint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickuint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickvoid (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickvoid (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickvoid (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fuextern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * Internal routines
c88420b3bc75201aa71e3c807fd31e66073a089fdmickstatic int pci_check(void);
843e19887f64dde75055cf8842fc4db2171eff45johnlev#if !defined(__xpv)
c88420b3bc75201aa71e3c807fd31e66073a089fdmickstatic int pci_check_bios(void);
c88420b3bc75201aa71e3c807fd31e66073a089fdmickstatic int pci_get_cfg_type(void);
137632774395dba0eb9b77257da1d8732bd5413dGuoli Shu/* for legacy io-based config space access */
137632774395dba0eb9b77257da1d8732bd5413dGuoli Shu/* for mmio-based config space access */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick/* ..except Orion and Neptune, which have to have their own */
7f58d7249497f31d23e7d0c4222d27998c8b0d38dilpreet mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * This code determines if this system supports PCI/PCIE and which
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * type of configuration access method is used
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * Only do this once. NB: If this is not a PCI system, and we
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * get called twice, we can't detect it and will probably die
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * horribly when we try to ask the BIOS whether PCI is present.
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * This code is safe *ONLY* during system startup when the
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * BIOS is still available.
843e19887f64dde75055cf8842fc4db2171eff45johnlev#if defined(__xpv)
843e19887f64dde75055cf8842fc4db2171eff45johnlev * only support PCI config mechanism 1 in i86xpv. This should be fine
843e19887f64dde75055cf8842fc4db2171eff45johnlev * since the other ones are workarounds for old broken H/W which won't
843e19887f64dde75055cf8842fc4db2171eff45johnlev * be supported in i86xpv anyway.
843e19887f64dde75055cf8842fc4db2171eff45johnlev * Since we can't get the BIOS info in i86xpv, we will do an
843e19887f64dde75055cf8842fc4db2171eff45johnlev * exhaustive search of all PCI buses. We have to do this until
843e19887f64dde75055cf8842fc4db2171eff45johnlev * we start using the PCI information in ACPI.
843e19887f64dde75055cf8842fc4db2171eff45johnlev#else /* !__xpv */
7b3700d1667b1178db936c8f0864fe50a502417eszhou pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * The BIOS for some systems with the Intel
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * Neptune chipset seem to default to #2 even
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * though the chipset can do #1. Override
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * the BIOS so that MP systems will work
c88420b3bc75201aa71e3c807fd31e66073a089fdmick * correctly.
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu#endif /* __xpv */
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * Try to get a valid mcfg_mem_base in early boot
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * If failed, leave mem-mapped pci config space accessing disabled
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu * until pci boot code (pci_autoconfig) makes sure this is a PCIE
c0da627439dfb642fb41ab7d78406fc69d2c64b2Zhi-Jun Robin Fu if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
843e19887f64dde75055cf8842fc4db2171eff45johnlev#if !defined(__xpv)
c88420b3bc75201aa71e3c807fd31e66073a089fdmick regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
c88420b3bc75201aa71e3c807fd31e66073a089fdmick /* the carry flag must not be set */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick /* ah (the high byte of ax) must be zero */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick default: /* ?!? */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick case 0: /* supports neither? */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick /* Check to see if the config mechanism has been set in /etc/system */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick /* call one of the PCI detection algorithms */
c88420b3bc75201aa71e3c807fd31e66073a089fdmick /* From pci_check() and pci_check_bios() */
843e19887f64dde75055cf8842fc4db2171eff45johnlev#endif /* __xpv */