Lines Matching refs:regs
252 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
257 dvname, reg, RTW_READ(regs, reg))
262 dvname, reg, RTW_READ16(regs, reg))
267 dvname, reg, RTW_READ8(regs, reg))
271 PRINTREG32(regs, RTW_IDR0);
272 PRINTREG32(regs, RTW_IDR1);
273 PRINTREG32(regs, RTW_MAR0);
274 PRINTREG32(regs, RTW_MAR1);
275 PRINTREG32(regs, RTW_TSFTRL);
276 PRINTREG32(regs, RTW_TSFTRH);
277 PRINTREG32(regs, RTW_TLPDA);
278 PRINTREG32(regs, RTW_TNPDA);
279 PRINTREG32(regs, RTW_THPDA);
280 PRINTREG32(regs, RTW_TCR);
281 PRINTREG32(regs, RTW_RCR);
282 PRINTREG32(regs, RTW_TINT);
283 PRINTREG32(regs, RTW_TBDA);
284 PRINTREG32(regs, RTW_ANAPARM);
285 PRINTREG32(regs, RTW_BB);
286 PRINTREG32(regs, RTW_PHYCFG);
287 PRINTREG32(regs, RTW_WAKEUP0L);
288 PRINTREG32(regs, RTW_WAKEUP0H);
289 PRINTREG32(regs, RTW_WAKEUP1L);
290 PRINTREG32(regs, RTW_WAKEUP1H);
291 PRINTREG32(regs, RTW_WAKEUP2LL);
292 PRINTREG32(regs, RTW_WAKEUP2LH);
293 PRINTREG32(regs, RTW_WAKEUP2HL);
294 PRINTREG32(regs, RTW_WAKEUP2HH);
295 PRINTREG32(regs, RTW_WAKEUP3LL);
296 PRINTREG32(regs, RTW_WAKEUP3LH);
297 PRINTREG32(regs, RTW_WAKEUP3HL);
298 PRINTREG32(regs, RTW_WAKEUP3HH);
299 PRINTREG32(regs, RTW_WAKEUP4LL);
300 PRINTREG32(regs, RTW_WAKEUP4LH);
301 PRINTREG32(regs, RTW_WAKEUP4HL);
302 PRINTREG32(regs, RTW_WAKEUP4HH);
303 PRINTREG32(regs, RTW_DK0);
304 PRINTREG32(regs, RTW_DK1);
305 PRINTREG32(regs, RTW_DK2);
306 PRINTREG32(regs, RTW_DK3);
307 PRINTREG32(regs, RTW_RETRYCTR);
308 PRINTREG32(regs, RTW_RDSAR);
309 PRINTREG32(regs, RTW_FER);
310 PRINTREG32(regs, RTW_FEMR);
311 PRINTREG32(regs, RTW_FPSR);
312 PRINTREG32(regs, RTW_FFER);
315 PRINTREG16(regs, RTW_BRSR);
316 PRINTREG16(regs, RTW_IMR);
317 PRINTREG16(regs, RTW_ISR);
318 PRINTREG16(regs, RTW_BCNITV);
319 PRINTREG16(regs, RTW_ATIMWND);
320 PRINTREG16(regs, RTW_BINTRITV);
321 PRINTREG16(regs, RTW_ATIMTRITV);
322 PRINTREG16(regs, RTW_CRC16ERR);
323 PRINTREG16(regs, RTW_CRC0);
324 PRINTREG16(regs, RTW_CRC1);
325 PRINTREG16(regs, RTW_CRC2);
326 PRINTREG16(regs, RTW_CRC3);
327 PRINTREG16(regs, RTW_CRC4);
328 PRINTREG16(regs, RTW_CWR);
331 PRINTREG8(regs, RTW_CR);
332 PRINTREG8(regs, RTW_9346CR);
333 PRINTREG8(regs, RTW_CONFIG0);
334 PRINTREG8(regs, RTW_CONFIG1);
335 PRINTREG8(regs, RTW_CONFIG2);
336 PRINTREG8(regs, RTW_MSR);
337 PRINTREG8(regs, RTW_CONFIG3);
338 PRINTREG8(regs, RTW_CONFIG4);
339 PRINTREG8(regs, RTW_TESTR);
340 PRINTREG8(regs, RTW_PSR);
341 PRINTREG8(regs, RTW_SCR);
342 PRINTREG8(regs, RTW_PHYDELAY);
343 PRINTREG8(regs, RTW_CRCOUNT);
344 PRINTREG8(regs, RTW_PHYADDR);
345 PRINTREG8(regs, RTW_PHYDATAW);
346 PRINTREG8(regs, RTW_PHYDATAR);
347 PRINTREG8(regs, RTW_CONFIG5);
348 PRINTREG8(regs, RTW_TPPOLL);
350 PRINTREG16(regs, RTW_BSSID16);
351 PRINTREG32(regs, RTW_BSSID32);
377 rtw_config0123_enable(struct rtw_regs *regs, int enable)
380 ecr = RTW_READ8(regs, RTW_9346CR);
385 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
388 RTW_WRITE8(regs, RTW_9346CR, ecr);
389 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
396 rtw_anaparm_enable(struct rtw_regs *regs, int enable)
400 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
406 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
407 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
417 struct rtw_regs *regs = &rsc->sc_regs;
419 anaparm = RTW_READ(regs, RTW_ANAPARM);
424 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
425 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
429 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
432 ASSERT(regs->r_access >= RTW_ACCESS_NONE &&
433 regs->r_access <= RTW_ACCESS_ANAPARM);
435 if (naccess == regs->r_access)
440 switch (regs->r_access) {
442 rtw_anaparm_enable(regs, 0);
445 rtw_config0123_enable(regs, 0);
452 switch (regs->r_access) {
454 rtw_config0123_enable(regs, 1);
459 rtw_anaparm_enable(regs, 0);
464 switch (regs->r_access) {
466 rtw_config0123_enable(regs, 1);
469 rtw_anaparm_enable(regs, 1);
479 rtw_set_access(struct rtw_regs *regs, enum rtw_access access)
481 rtw_set_access1(regs, access);
484 rtw_access_string(regs->r_access),
486 regs->r_access = access;
493 struct rtw_regs *regs = &rsc->sc_regs;
496 tcr = RTW_READ(regs, RTW_TCR);
502 RTW_WRITE(regs, RTW_TCR, tcr);
503 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
504 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
506 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
507 rtw_set_access(regs, RTW_ACCESS_NONE);
511 rtw_chip_reset1(struct rtw_regs *regs, const char *dvname)
516 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
518 RTW_WBR(regs, RTW_CR, RTW_CR);
521 cr = RTW_READ8(regs, RTW_CR);
527 RTW_RBR(regs, RTW_CR, RTW_CR);
536 rtw_chip_reset(struct rtw_regs *regs, const char *dvname)
538 RTW_WBW(regs, RTW_CR, RTW_TCR);
539 return (rtw_chip_reset1(regs, dvname));
543 rtw_disable_interrupts(struct rtw_regs *regs)
545 RTW_WRITE16(regs, RTW_IMR, 0);
546 RTW_WRITE16(regs, RTW_ISR, 0xffff);
547 (void) RTW_READ16(regs, RTW_IMR);
553 struct rtw_regs *regs = &rsc->sc_regs;
557 RTW_WRITE16(regs, RTW_IMR, rsc->sc_inten);
558 RTW_WRITE16(regs, RTW_ISR, 0xffff);
562 (*rsc->sc_intr_ack)(regs);
566 rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname)
571 ecr = RTW_READ8(regs, RTW_9346CR);
573 RTW_WRITE8(regs, RTW_9346CR, ecr);
575 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
579 ecr = RTW_READ8(regs, RTW_9346CR);
585 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
606 rtw_set_mode(struct rtw_regs *regs, int mode)
609 command = RTW_READ8(regs, RTW_9346CR);
614 RTW_WRITE8(regs, RTW_9346CR, command);
618 rtw_dma_start(struct rtw_regs *regs, int priority)
622 check = RTW_READ8(regs, RTW_TPPOLL);
625 RTW_WRITE8(regs, RTW_TPPOLL,
629 RTW_WRITE8(regs, RTW_TPPOLL,
633 RTW_WRITE8(regs, RTW_TPPOLL,
637 (void) RTW_READ8(regs, RTW_TPPOLL);
641 rtw_beacon_tx_disable(struct rtw_regs *regs)
645 rtw_set_mode(regs, RTW_EPROM_CMD_CONFIG);
646 RTW_WRITE8(regs, RTW_TPPOLL, mask);
647 rtw_set_mode(regs, RTW_EPROM_CMD_NORMAL);
656 struct rtw_regs *regs = &rsc->sc_regs;
659 (void) RTW_READ8(regs, RTW_CR);
790 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr,
799 ecr = RTW_READ8(regs, RTW_9346CR);
815 RTW_WRITE8(regs, RTW_9346CR, ecr);
832 sd.sd_handle = regs->r_handle;
833 sd.sd_base = regs->r_base;
861 RTW_WRITE8(regs, RTW_9346CR,
863 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
865 if ((rc = rtw_recall_eeprom(regs, dvname)) != 0)
883 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid,
889 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
911 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
913 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
917 RTW_READ8(regs, RTW_CONFIG4));
975 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale,
978 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0);
997 rtw_identify_sta(struct rtw_regs *regs, uint8_t *addr,
1000 uint32_t idr0 = RTW_READ(regs, RTW_IDR0),
1001 idr1 = RTW_READ(regs, RTW_IDR1);
1053 rtw_idle(struct rtw_regs *regs)
1059 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
1062 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ALL) != 0; active++)
1070 struct rtw_regs *regs = &rsc->sc_regs;
1075 cr = RTW_READ8(regs, RTW_CR);
1091 RTW_WRITE8(regs, RTW_CR, cr);
1092 (void) RTW_READ8(regs, RTW_CR);
1310 struct rtw_regs *regs = &rsc->sc_regs;
1315 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(phybaseaddr, hd_rx));
1316 RTW_WRITE(regs, RTW_TLPDA, RTW_RING_BASE(phybaseaddr, hd_txlo));
1317 RTW_WRITE(regs, RTW_TNPDA, RTW_RING_BASE(phybaseaddr, hd_txmd));
1318 RTW_WRITE(regs, RTW_THPDA, RTW_RING_BASE(phybaseaddr, hd_txhi));
1319 RTW_WRITE(regs, RTW_TBDA, RTW_RING_BASE(phybaseaddr, hd_bcn));
1320 rsc->hw_start = RTW_READ(regs, RTW_TNPDA);
1321 rsc->hw_go = RTW_READ(regs, RTW_TNPDA);
1421 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
1426 anaparm = RTW_READ(regs, RTW_ANAPARM);
1453 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
1454 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
1463 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
1468 anaparm = RTW_READ(regs, RTW_ANAPARM);
1495 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
1496 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
1500 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
1505 anaparm = RTW_READ(regs, RTW_ANAPARM);
1537 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
1538 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
1545 struct rtw_regs *regs = &rsc->sc_regs;
1547 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
1549 (*rsc->sc_pwrstate_cb)(regs, power, before_rf, digphy);
1551 rtw_set_access(regs, RTW_ACCESS_NONE);
1665 struct rtw_regs *regs = &rsc->sc_regs;
1691 RTW_WRITE(regs, RTW_MAR0, 0xffffffff);
1692 RTW_WRITE(regs, RTW_MAR1, 0xffffffff);
1694 RTW_WRITE(regs, RTW_RCR, rsc->sc_rcr);
1695 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
1699 RTW_READ(regs, RTW_MAR0),
1700 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR));
1701 RTW_WRITE(regs, RTW_RCR, rsc->sc_rcr);
1705 rtw_transmit_config(struct rtw_regs *regs)
1709 tcr = RTW_READ(regs, RTW_TCR);
1723 RTW_WRITE(regs, RTW_TCR, tcr);
1724 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
1730 struct rtw_regs *regs;
1733 regs = &rsc->sc_regs;
1738 rtw_beacon_tx_disable(regs);
1740 rtw_set_mode(regs, RTW_EPROM_CMD_CONFIG);
1742 rtw_transmit_config(regs);
1744 rtw_set_access(regs, RTW_ACCESS_CONFIG);
1745 RTW_WRITE(regs, RTW_TINT, 0xffffffff);
1746 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
1747 RTW_WRITE16(regs, RTW_BRSR, 0);
1749 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
1750 rtw_set_access(regs, RTW_ACCESS_NONE);
1751 RTW_WRITE(regs, RTW_FEMR, 0xffff);
1752 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
1753 rtw_set_rfprog(regs, rsc->sc_rfchipid, "rtw");
1755 RTW_WRITE8(regs, RTW_PHYDELAY, rsc->sc_phydelay);
1756 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
1757 rtw_set_mode(regs, RTW_EPROM_CMD_NORMAL);
1883 rtw_check_phydelay(struct rtw_regs *regs, uint32_t rcr0)
1890 RTW_WRITE(regs, RTW_RCR, REVAB);
1891 RTW_WBW(regs, RTW_RCR, RTW_RCR);
1892 RTW_WRITE(regs, RTW_RCR, REVC);
1894 RTW_WBR(regs, RTW_RCR, RTW_RCR);
1895 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
1898 RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */
1899 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
2347 struct rtw_regs *regs = &rsc->sc_regs;
2350 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
2352 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
2353 rtw_set_access(regs, RTW_ACCESS_CONFIG);
2355 RTW_WRITE8(regs, RTW_MSR, 0x8); /* sta mode link ok */
2358 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
2360 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
2361 RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND));
2362 RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV));
2364 rtw_set_access(regs, RTW_ACCESS_NONE);
2367 /* RTW_WRITE8(regs, RTW_SCR, 0); */
2787 struct rtw_regs *regs = &rsc->sc_regs;
2791 isr = RTW_READ16(regs, RTW_ISR);
2792 RTW_WRITE16(regs, RTW_ISR, isr);
2850 struct rtw_regs *regs = &rsc->sc_regs;
2853 rtw_disable_interrupts(regs);
2855 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2883 struct rtw_regs *regs;
2887 regs = &rsc->sc_regs;
2890 rtw_disable_interrupts(regs);
2892 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2967 struct rtw_regs *regs = &rsc->sc_regs;
2974 RTW_WRITE(regs, RTW_IDR0, ntohl(t));
2976 RTW_WRITE(regs, RTW_IDR1, ntohl(t));
2985 struct rtw_regs *regs = &rsc->sc_regs;
2994 RTW_WRITE(regs, RTW_RCR, rsc->sc_rcr);
3004 struct rtw_regs *regs = &rsc->sc_regs;
3012 RTW_WRITE(regs, RTW_MAR0, ntohl(t));
3014 RTW_WRITE(regs, RTW_MAR1, ntohl(t));
3015 RTW_WRITE(regs, RTW_RCR, rsc->sc_rcr);
3016 RTW_SYNC(regs, RTW_MAR0, RTW_RCR);
3019 RTW_WRITE(regs, RTW_MAR0, 0);
3020 RTW_WRITE(regs, RTW_MAR1, 0);
3021 RTW_WRITE(regs, RTW_RCR, rsc->sc_rcr);
3022 RTW_SYNC(regs, RTW_MAR0, RTW_RCR);