a72f7ea693101cc48bafbb4db6bb437d828011c4ql

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#include <sys/sysmacros.h>

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include <sys/pci.h>

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#include <sys/stat.h>

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include <sys/strsubr.h>

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#include <sys/strsun.h>

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#include <sys/mac_provider.h>

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include <sys/mac_wifi.h>

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#include <sys/net80211.h>

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer#include <sys/byteorder.h>

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include "rtwreg.h"

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include "rtwvar.h"

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include "smc93cx6var.h"

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include "rtwphy.h"

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include "rtwphyio.h"

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_device_acc_attr_t rtw_reg_accattr = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEVICE_ATTR_V0,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_STRUCTURE_LE_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_STRICTORDER_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEFAULT_ACC

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_device_acc_attr_t rtw_desc_accattr = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEVICE_ATTR_V0,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_NEVERSWAP_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_STRICTORDER_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEFAULT_ACC

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_device_acc_attr_t rtw_buf_accattr = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEVICE_ATTR_V0,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_NEVERSWAP_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_STRICTORDER_ACC,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DEFAULT_ACC

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_dma_attr_t dma_attr_desc = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DMA_ATTR_V0, /* dma_attr version */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x0000000000000000ull, /* dma_attr_addr_lo */

020c47705d28102a8df83a43ddf08e34dde21f22ql 0xFFFFFFFF, /* dma_attr_addr_hi */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFFFFFull, /* dma_attr_count_max */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x100, /* dma_attr_align */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFF, /* dma_attr_burstsizes */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000001, /* dma_attr_minxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFull, /* dma_attr_maxxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_sgllen */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_granular */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0 /* dma_attr_flags */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_dma_attr_t dma_attr_rxbuf = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DMA_ATTR_V0, /* dma_attr version */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x0000000000000000ull, /* dma_attr_addr_lo */

020c47705d28102a8df83a43ddf08e34dde21f22ql 0xFFFFFFFF, /* dma_attr_addr_hi */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFFFFFull, /* dma_attr_count_max */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (uint32_t)16, /* dma_attr_align */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFF, /* dma_attr_burstsizes */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000001, /* dma_attr_minxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFull, /* dma_attr_maxxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_sgllen */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_granular */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0 /* dma_attr_flags */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic ddi_dma_attr_t dma_attr_txbuf = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DMA_ATTR_V0, /* dma_attr version */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x0000000000000000ull, /* dma_attr_addr_lo */

020c47705d28102a8df83a43ddf08e34dde21f22ql 0xFFFFFFFF, /* dma_attr_addr_hi */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFFFFFull, /* dma_attr_count_max */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (uint32_t)16, /* dma_attr_align */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFF, /* dma_attr_burstsizes */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000001, /* dma_attr_minxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0x00000000FFFFull, /* dma_attr_maxxfer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_sgllen */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 1, /* dma_attr_granular */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0 /* dma_attr_flags */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void *rtw_soft_state_p = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Listatic void rtw_stop(void *);

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Listatic int rtw_attach(dev_info_t *, ddi_attach_cmd_t);

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Listatic int rtw_detach(dev_info_t *, ddi_detach_cmd_t);

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Listatic int rtw_quiesce(dev_info_t *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int rtw_m_stat(void *, uint_t, uint64_t *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int rtw_m_start(void *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void rtw_m_stop(void *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int rtw_m_promisc(void *, boolean_t);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int rtw_m_multicst(void *, boolean_t, const uint8_t *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int rtw_m_unicst(void *, const uint8_t *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic mblk_t *rtw_m_tx(void *, mblk_t *);

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void rtw_m_ioctl(void *, queue_t *, mblk_t *);

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Listatic int rtw_m_setprop(void *, const char *, mac_prop_id_t,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li uint_t, const void *);

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Listatic int rtw_m_getprop(void *, const char *, mac_prop_id_t,

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint_t, void *);

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerstatic void rtw_m_propinfo(void *, const char *, mac_prop_id_t,

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_handle_t);

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic mac_callbacks_t rtw_m_callbacks = {

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_stat,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_start,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_stop,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_promisc,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_multicst,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_unicst,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_m_tx,

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer NULL,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li rtw_m_ioctl,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li NULL, /* mc_getcapab */

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li NULL,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li NULL,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li rtw_m_setprop,

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer rtw_m_getprop,

0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer rtw_m_propinfo

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlDDI_DEFINE_STREAM_OPS(rtw_dev_ops, nulldev, nulldev, rtw_attach, rtw_detach,

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li nodev, NULL, D_MP, NULL, rtw_quiesce);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic struct modldrv rtw_modldrv = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql &mod_driverops, /* Type of module. This one is a driver */

9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li "realtek 8180L driver 1.7", /* short description */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql &rtw_dev_ops /* driver specific ops */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic struct modlinkage modlinkage = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql MODREV_1, (void *)&rtw_modldrv, NULL

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic uint32_t rtw_qlen[RTW_NTXPRI] = {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_TXQLENLO,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_TXQLENMD,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_TXQLENHI,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_TXQLENBCN

a72f7ea693101cc48bafbb4db6bb437d828011c4ql};

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

020c47705d28102a8df83a43ddf08e34dde21f22qluint32_t rtw_dbg_flags = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Listatic const struct ieee80211_rateset rtw_rateset_11b =

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li { 4, { 2, 4, 11, 22 } };

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li

a72f7ea693101cc48bafbb4db6bb437d828011c4ql_info(struct modinfo *modinfop)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (mod_info(&modlinkage, modinfop));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql_init(void)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int status;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql status = ddi_soft_state_init(&rtw_soft_state_p,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (rtw_softc_t), 1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (status != 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (status);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql mac_init_ops(&rtw_dev_ops, "rtw");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql status = mod_install(&modlinkage);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (status != 0) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql mac_fini_ops(&rtw_dev_ops);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_soft_state_fini(&rtw_soft_state_p);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (status);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql_fini(void)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int status;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql status = mod_remove(&modlinkage);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (status == 0) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql mac_fini_ops(&rtw_dev_ops);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_soft_state_fini(&rtw_soft_state_p);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (status);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql va_list args;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (dbg_flags & rtw_dbg_flags) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql va_start(args, fmt);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql vcmn_err(CE_CONT, fmt, args);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql va_end(args);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifdef DEBUG

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define PRINTREG32(sc, reg) \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_REGDUMP, \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: reg[ " #reg " / %03x ] = %08x\n", \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname, reg, RTW_READ(regs, reg))

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define PRINTREG16(sc, reg) \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_REGDUMP, \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: reg[ " #reg " / %03x ] = %04x\n", \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname, reg, RTW_READ16(regs, reg))

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define PRINTREG8(sc, reg) \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_REGDUMP, \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: reg[ " #reg " / %03x ] = %02x\n", \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname, reg, RTW_READ8(regs, reg))

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_REGDUMP, "%s: %s\n", dvname, where);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_IDR0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_IDR1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_MAR0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_MAR1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TSFTRL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TSFTRH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TLPDA);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TNPDA);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_THPDA);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_RCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TINT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_TBDA);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_BB);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_PHYCFG);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP0L);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP0H);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP1L);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP1H);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP2LL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP2LH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP2HL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP2HH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP3LL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP3LH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP3HL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP3HH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP4LL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP4LH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP4HL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_WAKEUP4HH);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_DK0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_DK1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_DK2);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_DK3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_RETRYCTR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_RDSAR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_FER);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_FEMR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_FPSR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_FFER);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* 16-bit registers */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_BRSR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_IMR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_ISR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_BCNITV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_ATIMWND);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_BINTRITV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_ATIMTRITV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC16ERR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC2);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CRC4);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_CWR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* 8-bit registers */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG2);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_MSR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG4);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_TESTR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_PSR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_SCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_PHYDELAY);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CRCOUNT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_PHYADDR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_PHYDATAW);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_PHYDATAR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_CONFIG5);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG8(regs, RTW_TPPOLL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG16(regs, RTW_BSSID16);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql PRINTREG32(regs, RTW_BSSID32);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#undef PRINTREG32

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#undef PRINTREG16

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#undef PRINTREG8

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* DEBUG */

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic const char *

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_access_string(enum rtw_access access)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (access) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_NONE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return ("none");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_CONFIG:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return ("config");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_ANAPARM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return ("anaparm");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return ("unknown");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_config0123_enable(struct rtw_regs *regs, int enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ecr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr = RTW_READ8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr |= RTW_9346CR_EEM_CONFIG;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql else {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr |= RTW_9346CR_EEM_NORMAL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_9346CR, ecr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_anaparm_enable(struct rtw_regs *regs, int enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t cfg3;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg3 = RTW_READ8(regs, RTW_CONFIG3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg3 |= RTW_CONFIG3_CLKRUNEN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg3 |= RTW_CONFIG3_PARMEN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql else

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg3 &= ~RTW_CONFIG3_PARMEN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_CONFIG3, cfg3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_txdac_enable(rtw_softc_t *rsc, int enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t anaparm;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *regs = &rsc->sc_regs;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql anaparm = RTW_READ(regs, RTW_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql anaparm &= ~RTW_ANAPARM_TXDACOFF;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql else

a72f7ea693101cc48bafbb4db6bb437d828011c4ql anaparm |= RTW_ANAPARM_TXDACOFF;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE(regs, RTW_ANAPARM, anaparm);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ASSERT(regs->r_access >= RTW_ACCESS_NONE &&

a72f7ea693101cc48bafbb4db6bb437d828011c4ql regs->r_access <= RTW_ACCESS_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (naccess == regs->r_access)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (naccess) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_NONE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (regs->r_access) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_ANAPARM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_anaparm_enable(regs, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*FALLTHROUGH*/

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_CONFIG:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_config0123_enable(regs, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*FALLTHROUGH*/

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_NONE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_CONFIG:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (regs->r_access) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_NONE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_config0123_enable(regs, 1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*FALLTHROUGH*/

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_CONFIG:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_ANAPARM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_anaparm_enable(regs, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_ANAPARM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (regs->r_access) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_NONE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_config0123_enable(regs, 1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*FALLTHROUGH*/

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_CONFIG:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_anaparm_enable(regs, 1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*FALLTHROUGH*/

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_ACCESS_ANAPARM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_set_access(struct rtw_regs *regs, enum rtw_access access)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_access1(regs, access);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ACCESS,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: access %s -> %s\n", __func__,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_access_string(regs->r_access),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_access_string(access));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql regs->r_access = access;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_continuous_tx_enable(rtw_softc_t *rsc, int enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *regs = &rsc->sc_regs;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t tcr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql tcr = RTW_READ(regs, RTW_TCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql tcr &= ~RTW_TCR_LBK_MASK;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql tcr |= RTW_TCR_LBK_CONT;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql else

a72f7ea693101cc48bafbb4db6bb437d828011c4ql tcr |= RTW_TCR_LBK_NORMAL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE(regs, RTW_TCR, tcr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_SYNC(regs, RTW_TCR, RTW_TCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_access(regs, RTW_ACCESS_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_txdac_enable(rsc, !enable);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_access(regs, RTW_ACCESS_ANAPARM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_access(regs, RTW_ACCESS_NONE);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_chip_reset1(struct rtw_regs *regs, const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t cr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBR(regs, RTW_CR, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < 1000; i++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cr = RTW_READ8(regs, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((cr & RTW_CR_RST) == 0) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_RESET,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: reset in %dus\n", dvname, i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RBR(regs, RTW_CR, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DELAY(10); /* 10us */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cmn_err(CE_WARN, "%s: reset failed\n", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (ETIMEDOUT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_chip_reset(struct rtw_regs *regs, const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBW(regs, RTW_CR, RTW_TCR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (rtw_chip_reset1(regs, dvname));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_disable_interrupts(struct rtw_regs *regs)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE16(regs, RTW_IMR, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE16(regs, RTW_ISR, 0xffff);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) RTW_READ16(regs, RTW_IMR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_enable_interrupts(rtw_softc_t *rsc)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *regs = &rsc->sc_regs;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->sc_inten = RTW_INTR_RX | RTW_INTR_TX | RTW_INTR_IOERROR;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE16(regs, RTW_IMR, rsc->sc_inten);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE16(regs, RTW_ISR, 0xffff);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* XXX necessary? */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (rsc->sc_intr_ack != NULL)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (*rsc->sc_intr_ack)(regs);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_recall_eeprom(struct rtw_regs *regs, const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ecr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr = RTW_READ8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_9346CR, ecr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBR(regs, RTW_9346CR, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* wait 25ms for completion */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < 250; i++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr = RTW_READ8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_RESET,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: recall EEPROM in %dus\n", dvname, i * 100);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RBR(regs, RTW_9346CR, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DELAY(100);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cmn_err(CE_WARN, "%s: recall EEPROM failed\n", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (ETIMEDOUT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_reset(rtw_softc_t *rsc)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int rc;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rc = rtw_chip_reset(&rsc->sc_regs, "rtw");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (rc != 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (rc);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) rtw_recall_eeprom(&rsc->sc_regs, "rtw");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_set_mode(struct rtw_regs *regs, int mode)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t command;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql command = RTW_READ8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql command = command &~ RTW_EPROM_CMD_OPERATING_MODE_MASK;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql command = command | (mode<<RTW_EPROM_CMD_OPERATING_MODE_SHIFT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql command = command &~ (1<<RTW_EPROM_CS_SHIFT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql command = command &~ (1<<RTW_EPROM_CK_SHIFT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_9346CR, command);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_dma_start(struct rtw_regs *regs, int priority)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t check = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql check = RTW_READ8(regs, RTW_TPPOLL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (priority) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case (0):

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_TPPOLL,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1<< RTW_TX_DMA_POLLING_LOWPRIORITY_SHIFT) | check);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case (1):

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_TPPOLL,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1<< RTW_TX_DMA_POLLING_NORMPRIORITY_SHIFT) | check);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case (2):

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_TPPOLL,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1<< RTW_TX_DMA_POLLING_HIPRIORITY_SHIFT) | check);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) RTW_READ8(regs, RTW_TPPOLL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_beacon_tx_disable(struct rtw_regs *regs)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t mask = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql mask |= (1 << RTW_TX_DMA_STOP_BEACON_SHIFT);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_mode(regs, RTW_EPROM_CMD_CONFIG);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_TPPOLL, mask);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_set_mode(regs, RTW_EPROM_CMD_NORMAL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_io_enable(rtw_softc_t *rsc, uint8_t flags, int enable);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_rtx_disable(rtw_softc_t *rsc)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *regs = &rsc->sc_regs;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_io_enable(rsc, RTW_CR_RE|RTW_CR_TE, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) RTW_READ8(regs, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_srom_free(struct rtw_srom *sr)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (sr->sr_content == NULL)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmem_free(sr->sr_content, sr->sr_size);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_size = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_content = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_rfchipid *rfchipid, uint32_t *rcr)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *rcr |= RTW_RCR_ENCS1;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *rfchipid = RTW_RFCHIPID_PHILIPS;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *rfname, *paname;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql char scratch[sizeof ("unknown 0xXX")];

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t version;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t mac[IEEE80211_ADDR_LEN];

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql version = RTW_SR_GET16(sr, RTW_SR_VERSION);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_IOSTATE, "%s: SROM version %d.%d", dvname,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql version >> 8, version & 0xff);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (version <= 0x0101) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cmn_err(CE_NOTE, " is not understood, limping along "

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "with defaults\n");

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < IEEE80211_ADDR_LEN; i++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: EEPROM MAC %s\n", dvname, mac);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *flags |= RTW_F_ANTDIV;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *flags |= RTW_F_DIGPHY;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *flags |= RTW_F_DFLANTB;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *rcr |= LSHIFT(MASK_AND_RSHIFT(RTW_SR_GET(sr, RTW_SR_RFPARM),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (*rfchipid) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_GCT: /* this combo seen in the wild */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = "GCT GRF5101";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql paname = "Winspring WS9901";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_MAXIM:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = "Maxim MAX2820"; /* guess */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql paname = "Maxim MAX2422"; /* guess */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_INTERSIL:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = "Intersil HFA3873"; /* guess */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql paname = "Intersil <unknown>";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = "Philips SA2400A";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql paname = "Philips SA2411";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_RFMD:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "LNA: RFMD RF2494, " /* mentioned in Realtek docs */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "SYN: Silicon Labs Si4126";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql paname = "RFMD RF2189"; /* mentioned in Realtek docs */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_RESERVED:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = paname = "reserved";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) snprintf(scratch, sizeof (scratch),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "unknown 0x%02x", *rfchipid);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rfname = paname = scratch;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_PHY, "%s: RF: %s, PA: %s\n",

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname, rfname, paname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_USA:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_USA;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_EUROPE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_EUROPE;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_JAPAN:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_JAPAN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_UNKNOWN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int rc;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct seeprom_descriptor sd;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ecr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) memset(&sd, 0, sizeof (sd));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr = RTW_READ8(regs, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((flags & RTW_F_9356SROM) != 0) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c56 SROM\n", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_size = 256;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_chip = C56_66;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql } else {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c46 SROM\n", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_size = 128;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_chip = C46;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ecr |= RTW_9346CR_EEM_PROGRAM;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_9346CR, ecr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_content = kmem_zalloc(sr->sr_size, KM_SLEEP);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (sr->sr_content == NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cmn_err(CE_WARN, "%s: unable to allocate SROM buffer\n",

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (ENOMEM);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) memset(sr->sr_content, 0, sr->sr_size);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_handle = regs->r_handle;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_base = regs->r_base;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_regsize = 1;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_control_offset = RTW_9346CR;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_status_offset = RTW_9346CR;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_dataout_offset = RTW_9346CR;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_CK = RTW_9346CR_EESK;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_CS = RTW_9346CR_EECS;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_DI = RTW_9346CR_EEDO;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_DO = RTW_9346CR_EEDI;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_MS = ecr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sd.sd_RDY = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cmn_err(CE_WARN, "%s: could not read SROM\n", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmem_free(sr->sr_content, sr->sr_size);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sr->sr_content = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (-1); /* XXX */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_9346CR,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((rc = rtw_recall_eeprom(regs, dvname)) != 0)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (rc);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifdef SROM_DEBUG

a72f7ea693101cc48bafbb4db6bb437d828011c4ql {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "\n%s: serial ROM:\n\t", dvname);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < sr->sr_size/2; i++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "offset-0x%x: %04x", 2*i, sr->sr_content[i]);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* DEBUG */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t cfg4;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *method;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (rfchipid) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg4 |= LSHIFT(0, RTW_CONFIG4_RFTYPE_MASK);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql method = "fallback";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_INTERSIL:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql method = "Intersil";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_PHILIPS:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql method = "Philips";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_GCT: /* XXX a guess */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_RFCHIPID_RFMD:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql method = "RFMD";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_CONFIG4, cfg4);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_INIT,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: %s RF programming method, %02x\n", dvname, method,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_READ8(regs, RTW_CONFIG4));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_init_channels(enum rtw_locale locale,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1],

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *name = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define ADD_CHANNEL(_chans, _chan) { \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (*_chans)[_chan].ich_flags = IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK;\

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (*_chans)[_chan].ich_freq = \

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ich_flags);\

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (locale) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_LOCALE_USA: /* 1-11 */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql name = "USA";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 1; i <= 11; i++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ADD_CHANNEL(chans, i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_LOCALE_JAPAN: /* 1-14 */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql name = "Japan";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ADD_CHANNEL(chans, 14);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 1; i <= 14; i++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ADD_CHANNEL(chans, i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_LOCALE_EUROPE: /* 1-13 */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql name = "Europe";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 1; i <= 13; i++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ADD_CHANNEL(chans, i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default: /* 10-11 allowed by most countries */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql name = "<unknown>";

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 10; i <= 11; i++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ADD_CHANNEL(chans, i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: Geographic Location %s\n",

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dvname, name);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql#undef ADD_CHANNEL

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_set80211props(struct ieee80211com *ic)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ic->ic_phytype = IEEE80211_T_DS;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ic->ic_opmode = IEEE80211_M_STA;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS |

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li IEEE80211_C_SHPREAMBLE;

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li /* IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li ic->ic_sup_rates[IEEE80211_MODE_11B] = rtw_rateset_11b;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql switch (cfg0 & RTW_CONFIG0_GL_MASK) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_USA:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_USA;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_JAPAN:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_JAPAN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql case RTW_CONFIG0_GL_EUROPE:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_EUROPE;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql default:

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *locale = RTW_LOCALE_UNKNOWN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql break;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_identify_sta(struct rtw_regs *regs, uint8_t *addr,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql const char *dvname)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t idr0 = RTW_READ(regs, RTW_IDR0),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql idr1 = RTW_READ(regs, RTW_IDR1);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *addr = MASK_AND_RSHIFT(idr0, BITS(0, 7));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *(addr + 1) = MASK_AND_RSHIFT(idr0, BITS(8, 15));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *(addr + 2) = MASK_AND_RSHIFT(idr0, BITS(16, 23));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *(addr + 3) = MASK_AND_RSHIFT(idr0, BITS(24, 31));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *(addr + 4) = MASK_AND_RSHIFT(idr1, BITS(0, 7));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *(addr + 5) = MASK_AND_RSHIFT(idr1, BITS(8, 15));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_ATTACH,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql "%s: 802.11mac address %x:%x:%x:%x:%x:%x\n", dvname,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql *addr, *(addr+1), *(addr+2), *(addr+3), *(addr+4), *(addr+5));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic uint8_t

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct ieee80211_channel *chan)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (RTW_SR_GET(sr, idx));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_rxdesc_init(rtw_softc_t *rsc, struct rtw_rxbuf *rbf, int idx, int is_last)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t ctl = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t *buf = (uint8_t *)rbf->bf_dma.mem_va;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ASSERT(rbf != NULL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rbf->rxdesc->rd_buf = (rbf->bf_dma.cookie.dmac_address);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql bzero(buf, rbf->bf_dma.alength);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DMA_SYNC(rbf->bf_dma, DDI_DMA_SYNC_FORDEV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ctl = (rbf->bf_dma.alength & 0xfff) | RTW_RXCTL_OWN;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (is_last)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ctl |= RTW_RXCTL_EOR;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rbf->rxdesc->rd_ctl = (ctl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* sync the mbuf */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* sync the descriptor */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DMA_SYNC_DESC(rsc->sc_desc_dma,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DESC_OFFSET(hd_rx, idx),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (struct rtw_rxdesc),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DMA_SYNC_FORDEV);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_idle(struct rtw_regs *regs)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int active;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* request stop DMA; wait for packets to stop transmitting. */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (active = 0; active < 300 &&

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ALL) != 0; active++)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql drv_usecwait(10);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_io_enable(rtw_softc_t *rsc, uint8_t flags, int enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t cr;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *regs = &rsc->sc_regs;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_IOSTATE, "%s: %s 0x%02x\n", __func__,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql enable ? "enable" : "disable", flags);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cr = RTW_READ8(regs, RTW_CR);

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* The receive engine will always start at RDSAR. */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable && (flags & ~cr & RTW_CR_RE)) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DMA_SYNC_DESC(rsc->sc_desc_dma,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DESC_OFFSET(hd_rx, 0),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (struct rtw_rxdesc),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DMA_SYNC_FORCPU);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->rx_next = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_rxdesc_init(rsc, rsc->rxbuf_h, 0, 0);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

94d05f6c7f329fdf908da99ab50b37d3d33f9fe5Qin Michael Li

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (enable)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cr |= flags;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql else

a72f7ea693101cc48bafbb4db6bb437d828011c4ql cr &= ~flags;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE8(regs, RTW_CR, cr);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) RTW_READ8(regs, RTW_CR);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bind_flags, dma_area_t *dma_p)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int err;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql err = ddi_dma_alloc_handle(devinfo, dma_attr,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (err != DDI_SUCCESS)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (DDI_FAILURE);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql &dma_p->alength, &dma_p->acc_hdl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (err != DDI_SUCCESS)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (DDI_FAILURE);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*

a72f7ea693101cc48bafbb4db6bb437d828011c4ql err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->mem_va, dma_p->alength, bind_flags,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if ((dma_p->ncookies != 1) || (err != DDI_DMA_MAPPED))

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (DDI_FAILURE);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->nslots = ~0U;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->size = ~0U;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->token = ~0U;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->offset = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql return (DDI_SUCCESS);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_free_dma_mem(dma_area_t *dma_p)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (dma_p->dma_hdl != NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (void) ddi_dma_unbind_handle(dma_p->dma_hdl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (dma_p->acc_hdl != NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_dma_mem_free(&dma_p->acc_hdl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->acc_hdl = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_dma_free_handle(&dma_p->dma_hdl);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->ncookies = 0;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_p->dma_hdl = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic void

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_dma_free(rtw_softc_t *rsc)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txbuf *txbf;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxbuf *rxbf;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i, j;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* Free TX DMA buffer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < RTW_NTXPRI; i++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf = list_head(&rsc->sc_txq[i].tx_free_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql while (txbf != NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_free_dma_mem(&txbf->bf_dma);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_remove(&rsc->sc_txq[i].tx_free_list, txbf);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf = list_head(&rsc->sc_txq[i].tx_free_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_destroy(&rsc->sc_txq[i].tx_free_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf = list_head(&rsc->sc_txq[i].tx_dirty_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql while (txbf != NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_free_dma_mem(&txbf->bf_dma);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_remove(&rsc->sc_txq[i].tx_dirty_list, txbf);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf = list_head(&rsc->sc_txq[i].tx_dirty_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_destroy(&rsc->sc_txq[i].tx_dirty_list);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (rsc->sc_txq[i].txbuf_h != NULL) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmem_free(rsc->sc_txq[i].txbuf_h,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (struct rtw_txbuf) * rtw_qlen[i]);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->sc_txq[i].txbuf_h = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* Free RX DMA buffer */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rxbf = rsc->rxbuf_h;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (j = 0; j < RTW_RXQLEN; j++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_free_dma_mem(&rxbf->bf_dma);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rxbf++;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (rsc->rxbuf_h != NULL) {

020c47705d28102a8df83a43ddf08e34dde21f22ql kmem_free(rsc->rxbuf_h,

020c47705d28102a8df83a43ddf08e34dde21f22ql sizeof (struct rtw_rxbuf) * RTW_RXQLEN);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->rxbuf_h = NULL;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql }

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_free_dma_mem(&rsc->sc_desc_dma);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql}

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4qlstatic int

a72f7ea693101cc48bafbb4db6bb437d828011c4qlrtw_dma_init(dev_info_t *devinfo, rtw_softc_t *rsc)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql{

a72f7ea693101cc48bafbb4db6bb437d828011c4ql int i, j, err;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql size_t size;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t buflen;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc *txds;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxdesc *rxds;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txbuf *txbf;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxbuf *rxbf;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t phybaseaddr, ptx[RTW_NTXPRI], prx;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql caddr_t virbaseaddr, vtx[RTW_NTXPRI], vrx;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* DMA buffer size for each TX/RX packet */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->sc_dmabuf_size = roundup(sizeof (struct ieee80211_frame) + 0x100 +

a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_MTU + IEEE80211_CRC_LEN + sizeof (struct ieee80211_llc) +

a72f7ea693101cc48bafbb4db6bb437d828011c4ql (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN +

a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_WEP_CRCLEN), rsc->sc_cachelsz);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql size = sizeof (struct rtw_descs);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql err = rtw_alloc_dma_mem(devinfo, &dma_attr_desc, size,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql &rtw_desc_accattr,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql &rsc->sc_desc_dma);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql if (err != DDI_SUCCESS)

a72f7ea693101cc48bafbb4db6bb437d828011c4ql goto error;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql phybaseaddr = rsc->sc_desc_dma.cookie.dmac_address;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql virbaseaddr = rsc->sc_desc_dma.mem_va;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ptx[0] = RTW_RING_BASE(phybaseaddr, hd_txlo);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ptx[1] = RTW_RING_BASE(phybaseaddr, hd_txmd);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ptx[2] = RTW_RING_BASE(phybaseaddr, hd_txhi);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql ptx[3] = RTW_RING_BASE(phybaseaddr, hd_bcn);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql vtx[0] = (caddr_t)(RTW_RING_BASE(virbaseaddr, hd_txlo));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql vtx[1] = (caddr_t)(RTW_RING_BASE(virbaseaddr, hd_txmd));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql vtx[2] = (caddr_t)(RTW_RING_BASE(virbaseaddr, hd_txhi));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql vtx[3] = (caddr_t)(RTW_RING_BASE(virbaseaddr, hd_bcn));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (i = 0; i < RTW_NTXPRI; i++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_DMA, "p[%d]=%x, v[%d]=%x", i, ptx[i],

a72f7ea693101cc48bafbb4db6bb437d828011c4ql i, vtx[i]);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_DPRINTF(RTW_DEBUG_DMA, "ring%d:", i);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_create(&rsc->sc_txq[i].tx_free_list,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (struct rtw_txbuf),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql offsetof(struct rtw_txbuf, bf_node));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_create(&rsc->sc_txq[i].tx_dirty_list,

a72f7ea693101cc48bafbb4db6bb437d828011c4ql sizeof (struct rtw_txbuf),

a72f7ea693101cc48bafbb4db6bb437d828011c4ql offsetof(struct rtw_txbuf, bf_node));

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* virtual address of the first descriptor */

020c47705d28102a8df83a43ddf08e34dde21f22ql rsc->sc_txq[i].txdesc_h =

020c47705d28102a8df83a43ddf08e34dde21f22ql (struct rtw_txdesc *)(uintptr_t)vtx[i];

a72f7ea693101cc48bafbb4db6bb437d828011c4ql

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txds = rsc->sc_txq[i].txdesc_h;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* allocate data structures to describe TX DMA buffers */

a72f7ea693101cc48bafbb4db6bb437d828011c4ql buflen = sizeof (struct rtw_txbuf) * rtw_qlen[i];

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf = (struct rtw_txbuf *)kmem_zalloc(buflen, KM_SLEEP);

a72f7ea693101cc48bafbb4db6bb437d828011c4ql rsc->sc_txq[i].txbuf_h = txbf;

a72f7ea693101cc48bafbb4db6bb437d828011c4ql for (j = 0; j < rtw_qlen[i]; j++, txbf++, txds++) {

a72f7ea693101cc48bafbb4db6bb437d828011c4ql txbf->txdesc = txds;

020c47705d28102a8df83a43ddf08e34dde21f22ql txbf->bf_daddr = ptx[i] + ((uintptr_t)txds -

020c47705d28102a8df83a43ddf08e34dde21f22ql (uintptr_t)rsc->sc_txq[i].txdesc_h);