Searched refs:outb (Results 1 - 25 of 85) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/
H A Dpic.c42 (void) outb(MCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
45 (void) outb(MIMR_PORT, PIC_VECTBASE);
48 (void) outb(MIMR_PORT, 1 << MASTERLINE);
51 (void) outb(MIMR_PORT, PIC_86MODE);
54 (void) outb(MIMR_PORT, 0xFF);
57 (void) outb(MCMD_PORT, PIC_READISR);
61 (void) outb(SCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4);
64 outb(SIMR_PORT, PIC_VECTBASE + 8);
67 outb(SIMR_PORT, MASTERLINE);
70 outb(SIMR_POR
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H A Di8237A.c195 outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);
214 outb(chan_addr[chnl].mask_reg, chnl & 3);
297 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);
302 outb(chan_addr[chnl].scm_reg, chnl);
389 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
472 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
496 outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */
515 outb(chan_addr[chnl].reqt_reg, chnl & 3); /* reset request bit */
607 outb(chan_addr[chnl].mode_reg, mode);
645 outb(chan_add
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/illumos-gate/usr/src/grub/grub-0.97/stage2/
H A Dhercules.c40 outb (unsigned short port, unsigned char value) function
42 asm volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port));
50 outb (HERCULES_INDEX_REG, 0x0f);
51 outb (0x80, 0);
52 outb (HERCULES_DATA_REG, offset & 0xFF);
53 outb (0x80, 0);
55 outb (HERCULES_INDEX_REG, 0x0e);
56 outb (0x80, 0);
57 outb (HERCULES_DATA_REG, offset >> 8);
58 outb (
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H A Dserial.c75 asm volatile ("outb %%al, $0x80" : : );
82 outb (unsigned short port, unsigned char value)
84 asm volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port));
85 asm volatile ("outb %%al, $0x80" : : );
112 outb (serial_hw_port + UART_TX, c);
118 outb (0x80, 0);
150 outb (port + UART_SR, UART_SR_TEST);
151 outb (port + UART_FCR, 0);
157 outb (port + UART_IER, 0);
160 outb (por
81 outb (unsigned short port, unsigned char value) function
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/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dns8390.c120 outb(src & 0xff, eth_asic_base + WD_GP2);
121 outb(src >> 8, eth_asic_base + WD_GP2);
123 outb(D8390_COMMAND_RD2 |
125 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
126 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
127 outb(src, eth_nic_base + D8390_P0_RSAR0);
128 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
129 outb(D8390_COMMAND_RD0 |
133 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
134 outb(sr
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H A Di386_timer.c29 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
31 outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT);
33 outb(ticks & 0xFF, TIMER2_PORT);
35 outb(ticks >> 8, TIMER2_PORT);
H A Drtl8139.c206 outb(0x00, nic->ioaddr + Config1);
263 outb(EE_ENB & ~EE_CS, ee_addr);
264 outb(EE_ENB, ee_addr);
270 outb(EE_ENB | dataval, ee_addr);
272 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
275 outb(EE_ENB, ee_addr);
279 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
282 outb(EE_ENB, ee_addr);
287 outb(~EE_CS, ee_addr);
314 outb(CmdRese
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H A Dvia-rhine.c748 outb (byMIICRbak & 0x7f, byMIICR);
751 outb (byMIIIndex, byMIIAD);
754 outb (inb (byMIICR) | 0x40, byMIICR);
768 outb (byMIIAdrbak, byMIIAD);
769 outb (byMIICRbak, byMIICR);
789 outb (byMIICRbak & 0x7f, byMIICR);
791 outb (byMIISetByte, byMIIAD);
794 outb (inb (byMIICR) | 0x40, byMIICR);
824 outb (inb (byMIICR) | 0x20, byMIICR);
835 outb (byMIIAdrba
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H A Dpic8259.h50 #define enable_irq(x) outb ( inb( IMR_REG(x) ) & ~IMR_BIT(x), IMR_REG(x) )
51 #define disable_irq(x) outb ( inb( IMR_REG(x) ) | IMR_BIT(x), IMR_REG(x) )
/illumos-gate/usr/src/uts/i86pc/dboot/
H A Ddboot_asm.h37 extern void outb(int port, uint8_t value);
H A Ddboot_asm.s41 outb(int port, uint8_t value)
69 * void outb(int port, uint8_t value)
71 ENTRY(outb) function
74 outb (%dx)
76 SET_SIZE(outb)
116 * void outb(int port, uint8_t value)
118 ENTRY_NP(outb)
121 outb (%dx)
123 SET_SIZE(outb)
/illumos-gate/usr/src/uts/i86pc/io/
H A Dmicrofind.c65 outb(PITCTL_PORT, PIT_C0 | PIT_LOADMODE | PIT_SQUAREMODE);
70 outb(PITCTR0_PORT, 0);
71 outb(PITCTR0_PORT, 0);
94 outb(PITCTL_PORT, PIT_LOADMODE);
99 outb(PITCTR0_PORT, 0xff);
100 outb(PITCTR0_PORT, 0xff);
111 outb(PITCTL_PORT, PIT_READBACK | PIT_READBACKC0);
H A Dtodpc_subr.c361 outb(RTC_ADDR, RTC_D); /* check if clock valid */
369 outb(RTC_ADDR, RTC_A); /* check if update in progress */
377 outb(RTC_ADDR, i);
380 outb(RTC_ADDR, century); /* do century */
384 outb(RTC_ADDR, day_alrm);
388 outb(RTC_ADDR, mon_alrm);
392 outb(RTC_ADDR, 0); /* re-read Seconds register */
422 outb(RTC_ADDR, RTC_B);
424 outb(RTC_ADDR, RTC_B);
425 outb(RTC_DAT
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/illumos-gate/usr/src/uts/i86pc/os/
H A Dpci_neptune.c61 outb(PCI_CSE_PORT, PCI_MECH2_CONFIG_ENABLE);
62 outb(PCI_FORW_PORT, 0);
76 outb(PCI_CSE_PORT, oldstatus);
81 outb(PCI_CSE_PORT, oldstatus);
101 outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
107 outb(PCI_PMC, neptune_BIOS_cfg_method);
111 outb(PCI_PMC, neptune_BIOS_cfg_method);
122 outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
135 outb(PCI_PMC, neptune_BIOS_cfg_method);
H A Dpci_mech2.c58 outb(PCI_CSE_PORT,
60 outb(PCI_FORW_PORT, bus);
68 outb(PCI_CSE_PORT, oldstatus);
129 outb(PCI_CADDR2(device, reg), val);
H A Dgraphics.c39 extern void outb(int, uchar_t);
58 outb(0x3c4, 2);
59 outb(0x3c5, plane);
65 outb(0x3ce, 8);
66 outb(0x3cf, value);
/illumos-gate/usr/src/boot/sys/boot/common/
H A Disapnp.c41 #define outb(x,y) (archsw.arch_isaoutb((x),(y))) macro
63 outb (_PNP_ADDRESS, d);
64 outb (_PNP_WRITE_DATA, r);
77 outb(_PNP_ADDRESS, 0);
78 outb(_PNP_ADDRESS, 0); /* yes, we do need it twice! */
81 outb(_PNP_ADDRESS, cur);
85 outb(_PNP_ADDRESS, cur);
98 outb(_PNP_ADDRESS, SERIAL_ISOLATION);
132 outb(_PNP_ADDRESS, STATUS);
142 outb(_PNP_ADDRES
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/illumos-gate/usr/src/uts/i86pc/boot/
H A Dboot_console.c159 outb(port + ISR, 0x20);
164 outb(port + DAT+7, 0x04); /* clear status */
165 outb(port + ISR, 0x40); /* set to bank 2 */
166 outb(port + MCR, 0x08); /* IMD */
167 outb(port + DAT, 0x21); /* FMD */
168 outb(port + ISR, 0x00); /* set to bank 0 */
176 outb(port + FIFOR, 0x00); /* clear */
177 outb(port + FIFOR, FIFO_ON); /* enable */
178 outb(port + FIFOR, FIFO_ON|FIFORXFLSH); /* reset */
179 outb(por
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H A Dboot_vga.c168 outb(VGA_COLOR_CRTC_INDEX, index);
169 outb(VGA_COLOR_CRTC_DATA, val);
175 outb(VGA_COLOR_CRTC_INDEX, index);
/illumos-gate/usr/src/uts/i86pc/ml/
H A Dcpr_wakecode.s286 outb (%dx)
292 outb (%dx)
315 outb (%dx)
321 outb (%dx)
332 outb (%dx)
338 outb (%dx)
356 outb (%dx)
362 outb (%dx)
387 outb (%dx)
393 outb (
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H A Dlocore.s370 outb $MCMD_PORT
382 outb $MIMR_PORT
434 outb $CYRIX_CRI
442 * effect of the above outb. We are reasonalbly confident that there
444 * no unpredictable side-effect of the above outb.
483 outb $CYRIX_CRI
486 outb $CYRIX_CRD
492 outb $CYRIX_CRI
500 outb $CYRIX_CRI
503 outb
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/illumos-gate/usr/src/boot/sys/boot/i386/libi386/
H A Drelocater_tramp.S155 outb %al,$0x20 # master,
156 outb %al,$0xa0 # slave
158 outb %al,$0x21 # master
160 outb %al,$0xa1 # slave
162 outb %al,$0x21 # master
164 outb %al,$0xa1 # slave
166 outb %al,$0x21 # master,
167 outb %al,$0xa1 # slave
169 outb %al,$0xa1 # IMR
171 outb
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/illumos-gate/usr/src/boot/sys/boot/i386/gptzfsboot/
H A Dsio.S32 outb %al,(%dx) # and DLAB
38 outb %al,(%dx) # DLAB
41 outb %al,(%dx) # DTR
67 outb %al,(%dx) # Write character
/illumos-gate/usr/src/uts/intel/io/
H A Dpit_beep.c268 outb(PITCTL_PORT, PIT_C2 | PIT_READMODE | PIT_RATEMODE);
269 outb(PITCTR2_PORT, counter & 0xff);
270 outb(PITCTR2_PORT, counter >> 8);
278 outb(PITAUX_PORT, inb(PITAUX_PORT) | (PITAUX_OUT2 | PITAUX_GATE2));
286 outb(PITAUX_PORT, inb(PITAUX_PORT) & ~(PITAUX_OUT2 | PITAUX_GATE2));
/illumos-gate/usr/src/uts/i86pc/io/psm/
H A Duppc.c268 outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE));
269 outb(PITCTR0_PORT, (uchar_t)clkticks);
270 outb(PITCTR0_PORT, (uchar_t)(clkticks>>8));
575 outb(SIMR_PORT, sp->smask);
576 outb(MIMR_PORT, sp->mmask);
965 outb(MCMD_PORT, PIC_NSEOI);
967 outb(SCMD_PORT, PIC_NSEOI);
972 outb(MCMD_PORT, PIC_NSEOI);
978 outb(MCMD_PORT, PIC_NSEOI);
979 outb(SCMD_POR
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