/* rhine.c:Fast Ethernet driver for Linux. */
/*
Adapted 09-jan-2000 by Paolo Marini (paolom@prisma-eng.it)
originally written by Donald Becker.
This software may be used and distributed according to the terms
of the GNU Public License (GPL), incorporated herein by reference.
Drivers derived from this code also fall under the GPL and must retain
this authorship and copyright notice.
Under no circumstances are the authors responsible for
the proper functioning of this software, nor do the authors assume any
responsibility for damages incurred with its use.
This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet
controller.
*/
/* A few user-configurable values. */
/* Size of the in-memory receive ring. */
/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
/* PCI Tuning Parameters
Threshold is bytes transferred to chip before transmission starts. */
/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */
/* Operational parameters that usually are not changed. */
/* Time in jiffies before concluding the transmitter is hung. */
#include "etherboot.h"
#include "nic.h"
#include "pci.h"
/* define all ioaddr */
/*--------------------- Exioaddr Definitions -------------------------*/
/*
* Bits in the RCR register
*/
/*
* Bits in the TCR register
*/
/*
* Bits in the CR0 register
*/
/*
* Bits in the CR1 register
*/
/*
* Bits in the CR register
*/
/*
* Bits in the IMR0 register
*/
/* define imrshadow */
/*
* Bits in the IMR1 register
*/
/*
* Bits in the ISR register
*/
/*
* Bits in the ISR0 register
*/
/*
* Bits in the ISR1 register
*/
/* ISR ABNORMAL CONDITION */
/*
* Bits in the MIISR register
*/
/*
* Bits in the MIICR register
*/
/*
* Bits in the EECSR register
*/
/*
* Bits in the BCR0 register
*/
/*
* Bits in the BCR1 register
*/
/*
* Bits in the CFGA register
*/
/*
* Bits in the CFGB register
*/
/*
* Bits in the CFGC register
*/
/*
* Bits in the CFGD register
*/
/* Bits in RSR */
/* Bits in TSR */
/* enabled mask value of irq */
/* Ethernet address filter type */
/* Loopback mode */
/* Transmit and receive descriptors definition */
struct rhine_tx_desc
{
union VTC_tx_status_tag
{
struct
{
}
bits;
unsigned long lw;
}
union VTC_tx_ctrl_tag
{
struct
{
}
bits;
unsigned long lw;
}
};
struct rhine_rx_desc
{
union VTC_rx_status_tag
{
struct
{
}
bits;
unsigned long lw;
}
union VTC_rx_ctrl_tag
{
struct
{
}
bits;
unsigned long lw;
}
};
/* The I/O extent. */
#ifdef HAVE_DEVLIST
#endif
/*
Theory of Operation
I. Board Compatibility
This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
controller.
II. Board-specific settings
Boards with this chip are functional only in a bus-master PCI slot.
Many operational settings are loaded from the EEPROM to the Config word at
offset 0x78. This driver assumes that they are correct.
If this driver is compiled to use PCI memory space operations the EEPROM
must be configured to enable memory ops.
III. Driver operation
IIIa. Ring buffers
This driver uses two statically allocated fixed-size descriptor lists
formed into rings by a branch from the final descriptor to the beginning of
the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
This driver attempts to use a zero-copy receive and transmit scheme.
Alas, all data buffers are required to start on a 32 bit boundary, so
the driver must often copy transmit packets into bounce buffers.
The driver allocates full frame size skbuffs for the Rx ring buffers at
open() time and passes the skb->data field to the chip as receive data
buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
a fresh skbuff is allocated and the frame is copied to the new skbuff.
When the incoming frame is larger, the skbuff is passed directly up the
protocol stack. Buffers consumed this way are replaced by newly allocated
skbuffs in the last phase of netdev_rx().
The RX_COPYBREAK value is chosen to trade-off the memory wasted by
using a full-sized skbuff for small frames vs. the copying costs of larger
frames. New boards are typically used in generously configured machines
and the underfilled buffers have negligible impact compared to the benefit of
a single allocation size, so the default value of zero results in never
copying packets. When copying is done, the cost is usually mitigated by using
most useful with small frames.
Since the VIA chips are only able to transfer data to buffers on 32 bit
boundaries, the the IP header at offset 14 in an ethernet frame isn't
longword aligned for further processing. Copying these unaligned buffers
has the beneficial effect of 16-byte aligning the IP header.
IIId. Synchronization
The driver runs as two independent, single-threaded flows of control. One
is the send-packet routine, which enforces single-threaded use by the
dev->tbusy flag. The other thread is the interrupt handler, which is single
threaded by the hardware and interrupt handling software.
The send packet thread has partial control over the Tx ring and 'dev->tbusy'
flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
queue slot is empty, it clears the tbusy flag when finished otherwise it sets
the 'lp->tx_full' flag.
The interrupt handler has exclusive control over the Rx ring and records stats
from the Tx ring. After reaping the stats, it marks the Tx queue entry as
empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
clears both the tx_full and tbusy flags.
IV. Notes
IVb. References
Preliminary VT86C100A manual from http://www.via.com.tw/
IVc. Errata
The VT86C100A manual is not reliable information.
The chip does not handle unaligned transmit or receive buffers, resulting
in significant performance degradation for bounce buffer copies on transmit
and unaligned IP headers on receive.
The chip does not pad to minimum transmit length.
*/
/* The rest of these values should never change. */
static struct rhine_private
{
const char *product_name;
/* temporary Rx buffers. */
int chip_id;
int chip_revision;
unsigned short ioaddr;
}
static int QueryAuto (int);
static int ReadMII (int byMIIIndex, int);
static void WriteMII (char, char, char, int);
static void MIIDelay (void);
unsigned int s, const char *p);
/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
static void
{
int i;
for (i = 0; i < RX_RING_SIZE; i++)
{
/* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */
}
/* Mark the last entry as wrapping the ring. */
/* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */
/*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */
/* The Tx buffer descriptor is filled in as needed, but we
do need to clear the ownership bit. */
for (i = 0; i < TX_RING_SIZE; i++)
{
/* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */
}
/* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */
}
int
{
int byMIIIndex;
int MIIReturn;
int negociated;
byMIIIndex = 0x04;
byMIIIndex = 0x05;
return 1;
else
return 0;
}
int
{
int ReturnMII;
char byMIIAdrbak;
char byMIICRbak;
char byMIItemp;
MIIDelay ();
MIIDelay ();
while (byMIItemp != 0)
{
}
MIIDelay ();
MIIDelay ();
return (ReturnMII);
}
void
{
int ReadMIItmp;
int MIIMask;
char byMIIAdrbak;
char byMIICRbak;
char byMIItemp;
MIIDelay ();
MIIDelay ();
while (byMIItemp != 0)
{
}
MIIDelay ();
MIIMask = 0x0001;
if (byMIIOP == 0)
{
}
else
{
}
MIIDelay ();
while (byMIItemp != 0)
{
}
MIIDelay ();
MIIDelay ();
}
void
MIIDelay (void)
{
int i;
for (i = 0; i < 0x7fff; i++)
{
inb (0x61);
inb (0x61);
inb (0x61);
inb (0x61);
}
}
/* Offsets to the device registers. */
enum register_offsets {
};
enum intr_status_bits {
};
/***************************************************************************
IRQ - PXE IRQ Handler
***************************************************************************/
/* Enable interrupts by setting the interrupt mask. */
unsigned int intr_status;
switch ( action ) {
case DISABLE :
case ENABLE :
/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
break;
case FORCE :
break;
}
}
static int
{
return 0;
rhine_reset (nic);
return 1;
}
unsigned char rx_mode;
/* ! IFF_PROMISC */
rx_mode = 0x0C;
}
static void
{
int i;
unsigned int timeout;
int FDXFlag;
if (rhine_debug > 0 && did_version++ == 0)
/* D-Link provided reset code (with comment additions) */
unsigned char byOrgValue;
if(rhine_debug > 0)
printf("Enabling Sticky Bit Workaround for Chip_id: 0x%hX\n"
, chip_id);
/* clear sticky bit before reset & read ethernet address */
/* (bits written are cleared?) */
/* disable force PME-enable */
/* disable power-event config bit */
/* clear power status (undocumented in vt6102 docs?) */
}
/* Perhaps this should be read from the EEPROM? */
for (i = 0; i < ETH_ALEN; i++)
/* restart MII auto-negotiation */
printf ("Analyzing Media type,this will take several seconds........");
for (i = 0; i < 5; i++)
{
/* need to wait 1 millisecond - we will round it up to 50-100ms */
/* nothing */;
break;
}
printf ("OK\n");
#if 0
/* JJM : for Debug */
{
}
#endif
/* query MII to know LineSpeed,duplex mode */
if (LineSpeed != 0) //JJM
{
printf ("Linespeed=10Mbs");
}
else
{
printf ("Linespeed=100Mbs");
}
if (FDXFlag == 1)
{
printf (" Fullduplex\n");
}
else
{
printf (" Halfduplex\n");
}
/* set MII 10 FULL ON */
/* turn on MII link change */
MIIDelay ();
MIIDelay ();
/* while((inb(byMIIAD)&0x20)==0) ; */
/* The lower four bits are the media type. */
if (options > 0)
{
if (tp->default_port)
}
return;
}
static void
{
/* merge reset and disable */
printf ("rhine disable\n");
/* Switch to loopback mode to avoid hardware races. */
/* Stop the chip's Tx and Rx processes. */
}
/**************************************************************************
ETH_RESET - Reset adapter
***************************************************************************/
static void
{
int i, j;
/* printf ("rhine_reset\n"); */
/* Soft reset the chip. */
/*outb(CmdReset, ioaddr + ChipCmd); */
tx_bufs_tmp = (int) buf1;
tx_ring_tmp = (int) desc1;
rx_bufs_tmp = (int) buf2;
rx_ring_tmp = (int) desc2;
/* tune RD TD 32 byte alignment */
/* printf ("txring[%d]", j); */
/* printf ("rxring[%X]", j); */
tx_bufs_tmp = (int) bus_to_virt (j);
/* printf ("txb[%X]", j); */
rx_bufs_tmp = (int) bus_to_virt (j);
/* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */
for (i = 0; i < RX_RING_SIZE; i++)
{
/* printf("r[%X]",tp->rx_buffs[i]); */
rx_bufs_tmp += 1536;
}
for (i = 0; i < TX_RING_SIZE; i++)
{
/* printf("t[%X]",tp->tx_buffs[i]); */
tx_bufs_tmp += 1536;
}
/* software reset */
MIIDelay ();
/* printf ("init ring"); */
/*write TD RD Descriptor to MAC */
/* Setup Multicast */
/* close IMR */
/* set TCR RCR threshold */
/* Set Fulldupex */
if (FDXFlag == 1)
{
}
/* KICK NIC to WORK */
/*set IMR to work */
}
/* Beware of PCI posted writes */
static int
{
{
unsigned int intr_status;
/* There is a packet ready */
if(!retreive)
return 1;
/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
#if 0
#endif
/* Acknowledge all of the current interrupt sources ASAP. */
if (intr_status & IntrTxDescRace)
{
printf("rhine_poll: bad status\n");
}
else if (rxstatus & (RSR_ABNORMAL))
{
}
else
good = 1;
if (good)
{
/* printf ("Packet RXed\n"); */
}
}
/* Acknowledge all of the current interrupt sources ASAP. */
return good;
}
static void
const char *d, unsigned int t, unsigned int s, const char *p)
{
int entry;
unsigned char CR1bak;
/*printf ("rhine_transmit\n"); */
/* setup ethernet header */
/* Calculate the next Tx descriptor entry. */
s += ETH_HLEN;
while (s < ETH_ZLEN)
/*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */
/*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */
/*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */
/*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */
/*printf("td1=[%X]",inl(dwCurrentTDSE0)); */
/*printf("td2=[%X]",inl(dwCurrentTDSE1)); */
/*printf("td3=[%X]",inl(dwCurrentTDSE2)); */
/*printf("td4=[%X]",inl(dwCurrentTDSE3)); */
/* Wait until transmit is finished */
;
/*outw(IMRShadow,byIMR0); */
/*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */
/*tp->tx_skbuff[entry] = 0; */
}
};
.type = NIC_DRIVER,
.name = "VIA 86C100",
.probe = rhine_probe,
.ids = rhine_nics,
.class = 0,
};
/* EOF via-rhine.c */