Lines Matching refs:outb
195 outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);
214 outb(chan_addr[chnl].mask_reg, chnl & 3);
297 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);
302 outb(chan_addr[chnl].scm_reg, chnl);
389 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
472 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
496 outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */
515 outb(chan_addr[chnl].reqt_reg, chnl & 3); /* reset request bit */
607 outb(chan_addr[chnl].mode_reg, mode);
645 outb(chan_addr[chnl].emode_reg, emode);
689 outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
692 outb(chan_addr[chnl].addr_reg, adr_byte[0]);
693 outb(chan_addr[chnl].addr_reg, adr_byte[1]);
694 outb(chan_addr[chnl].page_reg, adr_byte[2]);
696 outb(chan_addr[chnl].hpage_reg, adr_byte[3]);
720 outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
789 outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
792 outb(chan_addr[chnl].cnt_reg, count_byte[0]);
793 outb(chan_addr[chnl].cnt_reg, count_byte[1]);
795 outb(chan_addr[chnl].hcnt_reg, count_byte[2]);
819 outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */