Searched refs:inl (Results 1 - 25 of 40) sorted by relevance

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/illumos-gate/usr/src/lib/libkmf/libkmf/common/
H A Dpem_encode.c142 unsigned char *in, int inl)
148 if (inl == 0)
150 if ((ctx->num+inl) < ctx->length) {
151 (void) memcpy(&(ctx->enc_data[ctx->num]), in, inl);
152 ctx->num += inl;
159 inl -= i;
168 while (inl >= ctx->length) {
171 inl -= ctx->length;
178 if (inl != 0)
179 (void) memcpy(&(ctx->enc_data[0]), in, inl);
141 PEM_EncodeUpdate(PEM_ENCODE_CTX *ctx, unsigned char *out, int *outl, unsigned char *in, int inl) argument
322 PEM_DecodeUpdate(PEM_ENCODE_CTX *ctx, unsigned char *out, int *outl, unsigned char *in, int inl) argument
[all...]
/illumos-gate/usr/src/uts/i86pc/os/
H A Dpci_neptune.c73 if ((inl(PCI_CADDR2(0, PCI_CONF_VENID)) != 0x04a38086) ||
94 tmp = inl(PCI_CONFADD);
106 if (inl(PCI_CONFDATA) != ((0x04a3 << 16) | 0x8086)) {
H A Dpci_mech1.c92 val = inl(PCI_CONFDATA);
H A Dpci_mech2.c114 val = inl(PCI_CADDR2(device, reg));
H A Dpci_mech1_amd.c140 val = inl(PCI_CONFDATA);
/illumos-gate/usr/src/ucblib/libucb/port/gen/
H A Dnlist.c154 struct nlist *inl; local
160 for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nreq++)
366 struct nlist *p, *inl; local
389 for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nre
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/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dsis900.c210 if(inl(ee_addr) & EEGNT) {
282 rfcrSave = inl(rfcr + ioaddr);
363 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
431 #define eeprom_delay() inl(ee_addr)
474 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
486 #define sis900_mdio_delay() inl(mdio_addr)
537 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
612 outl(RxENA| inl(ioaddr + cr), ioaddr + cr);
635 outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr);
639 status ^= (inl(is
[all...]
H A Dnatsemi.c295 u32 chip_config = inl(ioaddr + ChipConfig);
304 nic_name, (int)inl(ioaddr + 0x84), advertising);
312 SavedClkRun = inl(ioaddr + ClkRun);
333 #define eeprom_delay(ee_addr) inl(ee_addr)
372 retval |= (inl(ee_addr) & EE_DataOut) ? 1 << i : 0;
391 return inl(ioaddr + 0x80 + (location<<2)) & 0xffff;
427 if (inl(ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */
462 if (inl(ioaddr + SiliconRev) == 0x302) {
515 inl(ioaddr + TxRingPtr));
549 inl(ioadd
[all...]
H A Ddavicom.c97 #define eeprom_delay() inl(ee_addr)
320 phy_data=(inl(ee_addr)>>19) & 0x1;
418 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
488 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
515 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
536 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
554 /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
638 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
641 (volatile unsigned long)inl(ioaddr + CSR8);
687 outl(inl(ioadd
[all...]
H A Dtulip.c361 #define eeprom_delay() inl(ee_addr)
549 #define mdio_delay() inl(mdio_addr)
580 inl(ioaddr + 0xA0);
581 inl(ioaddr + 0xA0);
583 if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
591 return inl(ioaddr + 0xB4 + (location<<2));
593 return inl(ioaddr + 0xD0);
595 return inl(ioaddr + 0xD4 + ((location-29)<<2));
620 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
641 if ( ! (inl(ioadd
[all...]
H A Dsundance.c412 outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl);
440 sdc->nic_name, (int) inl(BASE + RxStatus),
441 (int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0),
680 if (inl(BASE + ASICCtrl) & 0x80) {
705 dprintf(("ASIC Control is %x.\n", inl(BASE + ASICCtrl)));
707 dprintf(("ASIC Control is now %x.\n", inl(BASE + ASICCtrl)));
H A Dpcnet32.c350 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
362 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
373 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
383 inl(addr + PCNET32_DWIO_RESET);
389 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
H A D3c90x.c402 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
525 while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
912 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
H A D3c595.c142 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
373 vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG)
413 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
H A Depic100.c478 retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
502 if ((inl(mmctl) & MII_READOP) == 0)
H A Drtl8139.c249 #define eeprom_delay() inl(ee_addr)
406 txstatus = inl(nic->ioaddr+ TxStatus0 + cur_tx*4);
H A Dpci_io.c48 *value = inl(0xCFC);
/illumos-gate/usr/src/uts/i86pc/ml/
H A Damd64.il137 .inline inl,4
140 inl (%dx)
H A Dia32.il124 .inline inl,4
127 inl (%dx)
/illumos-gate/usr/src/uts/intel/asm/
H A Dsunddi.h68 inl(int port) function
74 "inl (%1)" /* value in %eax */
/illumos-gate/usr/src/cmd/mdb/intel/amd64/kmdb/
H A Dkmdb_asmutil.s145 4: inl (%dx)
/illumos-gate/usr/src/cmd/mdb/intel/ia32/kmdb/
H A Dkmdb_asmutil.s155 4: inl (%dx)
/illumos-gate/usr/src/uts/intel/sys/
H A Darchsystm.h105 extern uint32_t inl(int port);
/illumos-gate/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c522 return (ddi_swap32(inl((uintptr_t)addr)));
689 *h++ = ddi_swap32(inl(port));
692 *h++ = ddi_swap32(inl(port));
1030 val = inl((uintptr_t)addr);
1090 val = ddi_swap32(inl((uintptr_t)addr));
1295 if ((*h++ = inl(port)) == 0xffffffff)
1299 if ((*h++ = inl(port)) == 0xffffffff)
1479 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
1483 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
/illumos-gate/usr/src/uts/intel/ia32/ml/
H A Dddi_i86_asm.s407 inl (%dx)
436 inl (%dx)
1089 inl (%dx)
1097 inl (%dx)
1468 inl (%dx)
1502 inl (%dx)

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