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26a04d6751d8dbdcf709884101e1cb3d48723af2Dave Plauger * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Use is subject to license terms.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj/ Inline functions specific to the i86pc kernel running on bare metal.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Put a new value into cr3 (page table base register
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * void setcr3(void *value)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj/ disable interrupts and return value describing if interrupts were enabled
ae115bc77f6fcde83175c75b4206dc2e50747966mrj/ restore interrupt enable flag to value returned from 'clear_int_flag' above
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Invalidate TLB translation to 1 page.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * void mmu_tlbflush_entry(void *addr)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Call the halt instruction. This will put the CPU to sleep until
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * it is again awoken via an interrupt.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * This function should be called with interrupts already disabled
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * for the CPU.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Note that "sti" will only enable interrupts at the end of the
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * subsequent instruction...in this case: "hlt".
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * execute the bsrw instruction
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * int bsrw_insn(uint16_t)