Searched refs:GRCBASE_UPB (Results 1 - 4 of 4) sorted by relevance
| /illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/ |
| H A D | grc_addr.h | 27 #define GRCBASE_UPB 0x0C1000 macro
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| /illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ |
| H A D | ecore_init.h | 123 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
124 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
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| /illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
| H A D | bnxe_hw_debug.c | 687 // Read register GRCBASE_UPB + PB_REG_PB_INT_STS val and check if condition on val exist
688 IDLE_CHK_1(0x1F, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0), IDLE_CHK_ERROR, "UPB: Interrupt status is not 0");
999 // Read register GRCBASE_UPB + PB_REG_PB_PRTY_STS val and check if condition on val exist
1000 IDLE_CHK_1(0x1F, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "UPB: parity status is not 0");
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| H A D | lm_hw_attn.c | 171 REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0);
466 REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0x3);
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