d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * This file defines GRC base address for every block.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * This file is included by chipsim, asm microcode and cpp microcode.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * These values are used in Design.xml on regBase attribute
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * Use the base with the generated offsets of specific registers.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_PXPCS 0x000000 // this is the pciex core
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_TSDM 0x042000 //Note: regBase is made to fit in 20 bits, for TsdmTB::GrcCmd test
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_PXP 0x103000 // we have 2 pxp blocks now
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_PXP2 0x120000 // this is the 2nd pxp
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_QM_4PORT 0x168000 // a dummy block for generating 4-port-specific QM init values
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_TSEM 0x180000 // was previously GRCBASE_TSTORM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_CSEM 0x200000 // was previously GRCBASE_CSTORM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_XSEM 0x280000 // was previously GRCBASE_XSTORM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_XSEM_4PORT 0x280000 // a dummy block for generating 4-port-specific XSEM init values
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_USEM 0x300000 // was previously GRCBASE_USTORM
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define GRCBASE_MISC_AEU GRCBASE_MISC // just for driver init
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //_GRC_ADRR_H