Searched defs:GCPtrBase (Results 1 - 7 of 7) sorted by relevance
/vbox/include/VBox/vmm/ |
H A D | dbgfsel.h | 44 RTGCPTR GCPtrBase; member in struct:DBGFSELINFO
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/vbox/src/VBox/VMM/VMMR3/ |
H A D | PGMMap.cpp | 511 * @param GCPtrBase The address of the reserved range of guest memory. 512 * @param cb The size of the range starting at GCPtrBase. 514 VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb) argument 516 Log(("PGMR3MappingsFix: GCPtrBase=%RGv cb=%#x (fMappingsFixed=%RTbool MappingEnabled=%RTbool)\n", 517 GCPtrBase, cb, pVM->pgm.s.fMappingsFixed, pgmMapAreMappingsEnabled(pVM))); 534 return pgmR3MappingsFixInternal(pVM, GCPtrBase, cb); 551 * @param GCPtrBase The address of the reserved range of guest memory. 552 * @param cb The size of the range starting at GCPtrBase. 554 int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb) argument 559 AssertMsgReturn(!(GCPtrBase [all...] |
H A D | SELM.cpp | 2122 uint64_t GCPtrBase; local 2124 CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit); 2129 GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK); 2163 pSelInfo->GCPtrBase = 0; 2169 pSelInfo->GCPtrBase = X86DESC_BASE(&Desc); 2179 pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc); 2188 pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow 2197 pSelInfo->GCPtrBase = 0; 2225 pSelInfo->GCPtrBase = X86DESC_BASE(pDesc); 2232 pSelInfo->GCPtrBase 2309 uint64_t GCPtrBase; local [all...] |
/vbox/src/VBox/VMM/VMMAll/ |
H A D | IEMAllCImpl.cpp.h | 4154 RTGCPTR GCPtrBase; local 4160 GCPtrBase = pCtx->ldtr.u64Base; 4166 GCPtrBase = pCtx->gdtr.pGdt; 4170 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK)); 4179 rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8); 4382 RTGCPTR GCPtrBase; local 4383 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pIemCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize); 4387 rcStrict = CPUMSetGuestGDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit); 4392 pCtx->gdtr.pGdt = GCPtrBase; 4440 RTGCPTR GCPtrBase; local 4445 CPUMSetGuestIDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit); local [all...] |
H A D | CPUMAllRegs.cpp | 586 VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit) argument 595 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase; 600 VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit) argument 609 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
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H A D | IEMAll.cpp | 7343 static VBOXSTRICTRC iemMemStoreDataXdtr(PIEMCPU pIemCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, argument 7361 pu8Src[2] = RT_BYTE1(GCPtrBase); 7362 pu8Src[3] = RT_BYTE2(GCPtrBase); 7363 pu8Src[4] = RT_BYTE3(GCPtrBase); 7368 pu8Src[5] = RT_BYTE4(GCPtrBase); 7371 pu8Src[6] = RT_BYTE5(GCPtrBase); 7372 pu8Src[7] = RT_BYTE6(GCPtrBase); 7373 pu8Src[8] = RT_BYTE7(GCPtrBase); 7374 pu8Src[9] = RT_BYTE8(GCPtrBase); 8064 RTGCPTR GCPtrBase; local [all...] |
/vbox/src/VBox/Debugger/ |
H A D | DBGCEmulateCodeView.cpp | 2087 Sel, (unsigned)SelInfo.GCPtrBase, (unsigned)SelInfo.cbLimit); 2141 RTGCUINTPTR GCPtrBase = CPUMGetGuestIDTR(pVCpu, &cbLimit); local 2198 AddrVar.u.GCFlat = GCPtrBase + iInt * cbEntry; 3213 DBGCVAR_INIT_GC_FLAT(&VarTssAddr, SelInfo.GCPtrBase);
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