e1000g_sw.h revision 0dc2366f7b9f9f36e10909b1e95edbf2a261c2ac
0c27b3fe77ac1d5094ba3521e8142d9e7973133fMark Andrews * This file is provided under a CDDLv1 license. When using or
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * redistributing this file, you may do so under this license.
0c27b3fe77ac1d5094ba3521e8142d9e7973133fMark Andrews * In redistributing this file this license must be included
0c27b3fe77ac1d5094ba3521e8142d9e7973133fMark Andrews * and no other modification of this header file is permitted.
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * CDDL LICENSE SUMMARY
c1aef54e14bb92518b1c062ba8c0292a7cb949cbAutomatic Updater * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
ab023a65562e62b85a824509d829b6fad87e00b1Rob Austein * The contents of this file are subject to the terms of Version
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * 1.0 of the Common Development and Distribution License (the "License").
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * You should have received a copy of the License with this software.
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * You can obtain a copy of the License at
b1b3495eba72ea2b7270c5cd62b0bb824de74e05Mark Andrews * See the License for the specific language governing permissions
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews * and limitations under the License.
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington * Use is subject to license terms.
d999ca28d40337907b55eebc28a255b638702379Evan Hunt * **********************************************************************
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews * Module Name: *
d999ca28d40337907b55eebc28a255b638702379Evan Hunt * Abstract: *
fc14ca7a8f340f98884c504b3c4c3f40d7393fa9Mark Andrews * This header file contains Software-related data structures *
d999ca28d40337907b55eebc28a255b638702379Evan Hunt * definitions. *
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * **********************************************************************
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington/* Driver states */
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews#define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * + one for cross page split
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor +
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * two for the workaround of the 82546 chip
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * constants used in setting flow control thresholds
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews#define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews#define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256)
fc14ca7a8f340f98884c504b3c4c3f40d7393fa9Mark Andrews#define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256)
a903095bf4512dae561c7f6fc7854a51bebf334aMark Andrews#define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews /* which is normally 0x040 */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews#define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */
35f6a21f5f8114542c050bfcb484b39ce513d4bdEvan Hunt#define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews#define RX_DRAIN_TIME (200) /* # milliseconds recv drain */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define TX_STALL_TIME_2S (200) /* in unit of tick */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define TX_STALL_TIME_8S (800) /* in unit of tick */
bf33eb0b522801792a6663b0360bc94b9e9b77c2Automatic Updater * The size of the receive/transmite buffers
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews#define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015)
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * definitions for smartspeed workaround
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt /* or 30 seconds */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt#define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt /* or 6 seconds */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt * Definitions for module_info.
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt * Defined for IP header alignment. We also need to preserve space for
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt * VLAN tag (4 bytes)
d999ca28d40337907b55eebc28a255b638702379Evan Hunt * bit flags for 'attach_progress' which is a member variable in struct e1000g
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */
d999ca28d40337907b55eebc28a255b638702379Evan Hunt#define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt/* 0200 used to be PROGRESS_NDD. Now unused */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt#define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt#define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt#define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */
baad8d9fd8dd054ce1edf350ff0c0f2038a1519eEvan Hunt * Speed and Duplex Settings
3d17a3ba61a303d5c4d9867068d0fbe9f24d2988Mark Andrews * Coexist Workaround RP: 07/04/03
3d17a3ba61a303d5c4d9867068d0fbe9f24d2988Mark Andrews * 82544 Workaround : Co-existence
3d17a3ba61a303d5c4d9867068d0fbe9f24d2988Mark Andrews * Defines for Jumbo Frame
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews/* Defines for Tx stall check */
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews/* Defines for DVMA */
2c15fcdeac4c2402258867fbac24d7475ef98259Mark Andrews * Loopback definitions
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * Private dip list definitions
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * Tx descriptor LENGTH field mask
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews * not remove the head from the queue.
dc6da18ccbb808d21f123cc6bda399b44ad11445Mark Andrews#define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink))
2c15fcdeac4c2402258867fbac24d7475ef98259Mark Andrews * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
26bb3b7a67b833f0a18072567de036226890ca1aMark Andrews * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list),
26bb3b7a67b833f0a18072567de036226890ca1aMark Andrews * and return it (this differs from QUEUE_REMOVE_HEAD only in
26bb3b7a67b833f0a18072567de036226890ca1aMark Andrews * the 1st line).
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
c5223c9cb7c22620d5ee6611228673e95b48a270Mark Andrews * remove the tail from the queue.
bf33eb0b522801792a6663b0360bc94b9e9b77c2Automatic Updater#define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink))
a903095bf4512dae561c7f6fc7854a51bebf334aMark Andrews * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
35f6a21f5f8114542c050bfcb484b39ce513d4bdEvan Hunt * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
d999ca28d40337907b55eebc28a255b638702379Evan Hunt * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * current element.
92551304a9abff9284de5b79a48e83d781989339Mark Andrews (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
92551304a9abff9284de5b79a48e83d781989339Mark Andrews (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
92551304a9abff9284de5b79a48e83d781989339Mark Andrews (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \
b6a4cc6927f45f202826c4dc6bb29cd8aeba90efTatuya JINMEI 神明達哉 * Property lookups
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman * E1000G-specific ioctls ...
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman#define E1000G_IOC ((((((('E' << 4) + '1') << 4) \
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman * These diagnostic IOCTLS are enabled only in DEBUG drivers
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman#define E1000G_IOC_REG_PEEK (E1000G_IOC | 1)
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman#define E1000G_IOC_REG_POKE (E1000G_IOC | 2)
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman#define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3)
ab023a65562e62b85a824509d829b6fad87e00b1Rob Austein#define E1000G_PP_SPACE_REG 0 /* PCI memory space */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrewstypedef struct {
45e1bd63587102c3bb361eaca42ee7b714fb3542Mark Andrews uint64_t pp_acc_space; /* See #defines below */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews uint64_t pp_acc_offset; /* See regs definition */
b6a4cc6927f45f202826c4dc6bb29cd8aeba90efTatuya JINMEI 神明達哉 uint64_t pp_acc_data; /* output for peek */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews /* input for poke */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews#endif /* E1000G_DEBUG */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * (Internal) return values from ioctl subroutines
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaraman * Named Data (ND) Parameter Management Structure
0c29904b27c9ab3b85ecbde159b22ae1323bdbcdMukund Sivaramantypedef struct {
b6a4cc6927f45f202826c4dc6bb29cd8aeba90efTatuya JINMEI 神明達哉 * The entry of the private dip list
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * A structure that points to the next entry in the queue.
3bc4221346e5045c5679dd0d84f4f7d888a9da79Mark Andrews * A "ListHead" structure that points to the head and tail of a queue
3bc4221346e5045c5679dd0d84f4f7d888a9da79Mark Andrewstypedef struct _LIST_DESCRIBER {
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrewstypedef struct {
0f8c9b5eed7e8714ceb7d6d3675555df9c5f6350Mark Andrews * Address-Length pair structure that stores descriptor info
c4abb197160a74f7cd4ad23ebc63fbe0194010abEvan Hunttypedef struct _sw_desc {
c4abb197160a74f7cd4ad23ebc63fbe0194010abEvan Hunttypedef struct _desc_array {
c4abb197160a74f7cd4ad23ebc63fbe0194010abEvan Hunttypedef enum {
c4abb197160a74f7cd4ad23ebc63fbe0194010abEvan Hunttypedef struct _dma_buffer {
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * Transmit Control Block (TCB), Ndis equiv of SWPacket This
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * structure stores the additional information that is
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * associated with every packet to be transmitted. It stores the
92551304a9abff9284de5b79a48e83d781989339Mark Andrews * message block pointer and the TBD addresses associated with
e9359db5e958bf05f9b9c5fe3c27d533f0f05550Mark Andrews * the m_blk and also the link to the next tcb in the chain
7791dd06ea69d0fb2494788ad4c24d568f40bcdfMark Andrewstypedef struct _tx_sw_packet {
7791dd06ea69d0fb2494788ad4c24d568f40bcdfMark Andrews /* Link to the next tx_sw_packet in the list */
3bc4221346e5045c5679dd0d84f4f7d888a9da79Mark Andrews * This structure is similar to the rx_sw_packet structure used
3bc4221346e5045c5679dd0d84f4f7d888a9da79Mark Andrews * for Ndis. This structure stores information about the 2k
3bc4221346e5045c5679dd0d84f4f7d888a9da79Mark Andrews * aligned receive buffer into which the FX1000 DMA's frames.
a26ad011f382d12058478704cb5e90e6f4366d01Andreas Gustafsson * This structure is maintained as a linked list of many
a26ad011f382d12058478704cb5e90e6f4366d01Andreas Gustafsson * receiver buffer pointers.
ff6de396a93b9b73a37173059a595f3d295b57cbMark Andrews /* Link to the next rx_sw_packet_t in the list */
0f8c9b5eed7e8714ceb7d6d3675555df9c5f6350Mark Andrewstypedef struct _mblk_list {
0f8c9b5eed7e8714ceb7d6d3675555df9c5f6350Mark Andrewstypedef struct _context_data {
1b42401954a8770d82a168ae1ac06ce66862fd25Mark Andrewstypedef struct _e1000g_stat {
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t rx_error; /* Rx Error in Packet */
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t rx_size_error; /* Rx Size Error */
e9472e9f18f1c4f1279be2b3147be13a2bb731d0Mark Andrews kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */
66a38d16933a28a0110079a9920ba359d2aad130Danny Mayer kstat_named_t tx_send_fail; /* Tx SendPkt Failure */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t tx_over_size; /* Tx Pkt Too Long */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t tx_reschedule; /* Tx Reschedule */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t rx_none; /* Rx No Incoming Data */
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */
c2bc56dc65b4b103a5600565680eb5f33fa4c90bMark Andrews kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */
cda18e781315e9bc4f7ca161eb2ded5a45675bcfAndreas Gustafsson kstat_named_t tx_under_size; /* Tx Packet Under Size */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t tx_empty_frags; /* Tx Empty Frags */
fc14ca7a8f340f98884c504b3c4c3f40d7393fa9Mark Andrews kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */
92551304a9abff9284de5b79a48e83d781989339Mark Andrews kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */
ff6de396a93b9b73a37173059a595f3d295b57cbMark Andrews kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */
8d0ee7a153381d98f6c1e6e9bfe6b73659433666Brian Wellington kstat_named_t tx_lack_desc; /* Tx Lack of Desc */
ed6ca94ad75353d5344e2a456e7a8beb480a351fMark Andrews kstat_named_t Symerrs; /* Symbol Error Count */
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews kstat_named_t Scc; /* Single Collision Count */
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t Ecol; /* Excessive Collision Count */
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t Mcc; /* Multiple Collision Count */
77b101ced9801cdb226919784bfc1aa0650ace6aMark Andrews kstat_named_t Latecol; /* Late Collision Count */
1b42401954a8770d82a168ae1ac06ce66862fd25Mark Andrews kstat_named_t Rlec; /* Receive Length Error Count */
cda18e781315e9bc4f7ca161eb2ded5a45675bcfAndreas Gustafsson kstat_named_t Xoffrxc; /* XOFF Received Count */
7e8c1a13e97448db2ec17d05c4917939a12aa9c0Mark Andrews kstat_named_t Xofftxc; /* Xoff Xmitted Count */
#ifdef E1000G_DEBUG
#ifdef E1000G_DEBUG
typedef struct _e1000g_tx_ring {
#ifdef E1000G_DEBUG
typedef struct _e1000g_rx_data {
typedef struct _e1000g_rx_ring {
#ifdef E1000G_DEBUG
typedef struct e1000g {
int instance;
#ifdef __sparc
int intr_type;
int intr_cnt;
int intr_cap;
int tx_softint_pri;
int fm_capabilities;
} e1000g_t;
extern int e1000g_poll_mode;
#ifdef __cplusplus