Searched refs:Enable (Results 1 - 25 of 116) sorted by relevance

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/vbox/src/VBox/Additions/WINNT/Graphics/Video/mp/common/
H A DVBoxMPCommon.h58 pAttrs->Enable & 0x0000FFFF,
59 (pAttrs->Enable >> 16) & 0xFF,
60 (pAttrs->Enable >> 24) & 0xFF,
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Library/
H A DIoApicLib.h58 @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
65 IN BOOLEAN Enable
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Core/Dxe/Event/
H A DTpl.c21 @param Enable The state of enable or disable interrupt
26 IN BOOLEAN Enable
35 if (!Enable) {
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/
H A DPciOptionRomSupport.h112 Enable/Disable Option Rom decode.
118 @param Enable Flag for enable/disable decode.
126 IN BOOLEAN Enable
H A DPciOptionRomSupport.c431 // Enable RomBar
556 Enable/Disable Option Rom decode.
562 @param Enable Flag for enable/disable decode.
570 IN BOOLEAN Enable
579 if (Enable) {
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Universal/Network/SnpDxe/
H A DReceive_filters.c298 * The filter mask bits that are set (ON) in the Enable parameter are added to
304 If the same bits are set in the Enable and Disable parameters, then the bits
308 Enable and Disable parameters). The SNP->Mode->MCastFilterCount field is set
340 @param Enable A bit mask of receive filters to enable on the network
362 * There are bits set in Enable that are not set
368 set in Enable, it is not set in Disable, and
390 IN UINT32 Enable,
425 if (((Enable &~Snp->Mode.ReceiveFilterMask) != 0) ||
447 if (Enable == 0 && Disable == 0 && !ResetMCastFilter && MCastFilterCnt == 0) {
452 if ((Enable
388 SnpUndi32ReceiveFilters( IN EFI_SIMPLE_NETWORK_PROTOCOL *This, IN UINT32 Enable, IN UINT32 Disable, IN BOOLEAN ResetMCastFilter, IN UINTN MCastFilterCnt, OPTIONAL IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL ) argument
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H A DCallback.c91 @param Enable Non-zero indicates acquire; Zero indicates release.
97 IN UINT32 Enable
109 if (Enable != 0) {
242 @param Enable Non-zero indicates acquire; Zero indicates release.
249 IN UINT32 Enable
259 if (Enable != 0) {
H A DSnp.h293 @param Enable non-zero indicates acquire
300 IN UINT32 Enable
378 @param Enable non-zero indicates acquire
385 IN UINT32 Enable
656 * The filter mask bits that are set (ON) in the Enable parameter are added to
662 If the same bits are set in the Enable and Disable parameters, then the bits
666 Enable and Disable parameters). The SNP->Mode->MCastFilterCount field is set
698 @param Enable A bit mask of receive filters to enable on the network
720 * There are bits set in Enable that are not set
726 set in Enable, i
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/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Arm/
H A DEnableInterrupts.S34 bic R0,R0,#0x80 @Enable IRQ interrupts
H A DEnableInterrupts.asm33 BIC R0,R0,#0x80 ;Enable IRQ interrupts
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/BaseIoApicLib/
H A DIoApicLib.c77 @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
84 IN BOOLEAN Enable
95 Entry.Bits.Mask = Enable ? 0 : 1;
/vbox/src/VBox/HostServices/SharedOpenGL/crserverlib/
H A Dserver_clear.c337 cr_server.head_spu->dispatch_table.Enable(GL_BLEND);
382 cr_server.head_spu->dispatch_table.Enable(GL_BLEND);
408 cr_server.head_spu->dispatch_table.Enable(GL_LIGHTING);
410 cr_server.head_spu->dispatch_table.Enable(GL_FOG);
412 cr_server.head_spu->dispatch_table.Enable(GL_TEXTURE_1D);
414 cr_server.head_spu->dispatch_table.Enable(GL_TEXTURE_2D);
416 cr_server.head_spu->dispatch_table.Enable(GL_TEXTURE_3D);
418 cr_server.head_spu->dispatch_table.Enable(GL_CULL_FACE);
/vbox/src/VBox/Additions/WINNT/Graphics/Wine/include/
H A Dshldisp.idl56 HRESULT Enable( [in] BOOL fEnable );
/vbox/src/VBox/GuestHost/OpenGL/state_tracker/
H A Dstate_diff.c171 diff_api.Enable(GL_DEPTH_TEST);
186 diff_api.Enable(GL_STENCIL_TEST);
318 diff_api.Enable(GL_DEPTH_TEST);
330 diff_api.Enable(GL_STENCIL_TEST);
407 diff_api.Enable(GL_ALPHA_TEST);
411 diff_api.Enable(GL_SCISSOR_TEST);
415 diff_api.Enable(GL_BLEND);
419 diff_api.Enable(GL_COLOR_LOGIC_OP);
423 diff_api.Enable(GL_DEPTH_TEST);
427 diff_api.Enable(GL_STENCIL_TES
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H A Dstate_point.c219 able[1] = diff_api.Enable;
286 able[1] = diff_api.Enable;
330 able[1] = diff_api.Enable;
406 diff_api.Enable(GL_POINT_SPRITE_ARB);
430 able[1] = diff_api.Enable;
443 able[1] = diff_api.Enable;
/vbox/src/VBox/Additions/WINNT/Graphics/Video/disp/xpdm/
H A DVBoxDispMouse.cpp379 pDev->pointer.pAttrs->Enable = 0;
483 * Note: pDev->pointer.pAttrs->Enable is also used to pass hotspot coordinates in it's high word
489 pDev->pointer.pAttrs->Enable = VBOX_MOUSE_POINTER_SHAPE;
490 pDev->pointer.pAttrs->Enable |= (yHot & 0xFF) << 24;
491 pDev->pointer.pAttrs->Enable |= (xHot & 0xFF) << 16;
495 pDev->pointer.pAttrs->Enable |= VBOX_MOUSE_POINTER_VISIBLE;
500 pDev->pointer.pAttrs->Enable |= VBOX_MOUSE_POINTER_ALPHA;
/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Include/Protocol/
H A DIsaAcpi.h233 @param[in] Enable TRUE to enable the ISA controller. FALSE to disable the
245 IN BOOLEAN Enable
/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Library/
H A DUefiRuntimeLib.h149 @param Enable Enable or disable the wakeup alarm.
150 @param Time If Enable is TRUE, the time to set the wakeup alarm for. Type EFI_TIME
151 is defined in the GetTime() function description. If Enable is FALSE,
154 @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled.
155 If Enable is FALSE, then the wakeup alarm was disabled.
164 IN BOOLEAN Enable,
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/IsaAcpiDxe/
H A DPcatIsaAcpi.h219 Enable/Disable the specific ISA device.
223 @param Enable Enable/Disable
233 IN BOOLEAN Enable
H A DIsaAcpi.c304 Enable/Disable the specific ISA device.
308 @param Enable Enable/Disable
318 IN BOOLEAN Enable
/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library/UefiRuntimeLib/
H A DRuntimeLib.c354 @param Enable Enable or disable the wakeup alarm.
355 @param Time If Enable is TRUE, the time to set the wakeup alarm for. Type EFI_TIME
356 is defined in the GetTime() function description. If Enable is FALSE,
359 @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled.
360 If Enable is FALSE, then the wakeup alarm was disabled.
369 IN BOOLEAN Enable,
373 return mInternalRT->SetWakeupTime (Enable, Time);
368 EfiSetWakeupTime( IN BOOLEAN Enable, IN EFI_TIME *Time OPTIONAL ) argument
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/
H A DPcRtc.h104 UINT8 Sqwe : 1; // 0 - Disable SQWE output 1 - Enable SQWE output
202 @param Enabled Enable or disable the wakeup alarm.
203 @param Time If Enable is TRUE, the time to set the wakeup alarm for.
204 If Enable is FALSE, then this parameter is optional, and may be NULL.
207 @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled.
208 If Enable is FALSE, then the wakeup alarm was disabled.
216 IN BOOLEAN Enable,
H A DPcRtc.c557 @param Enabled Enable or disable the wakeup alarm.
558 @param Time If Enable is TRUE, the time to set the wakeup alarm for.
559 If Enable is FALSE, then this parameter is optional, and may be NULL.
562 @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled.
563 If Enable is FALSE, then the wakeup alarm was disabled.
571 IN BOOLEAN Enable,
584 if (Enable) {
637 if (Enable) {
570 PcRtcSetWakeupTime( IN BOOLEAN Enable, IN EFI_TIME *Time, OPTIONAL IN PC_RTC_MODULE_GLOBALS *Global ) argument
/vbox/src/VBox/Additions/WINNT/Graphics/Video/mp/wddm/
H A DVBoxMPVbva.cpp211 memset(&pCtl->Enable, 0, sizeof (pCtl->Enable));
212 pCtl->Enable.u32Flags = fEnable? VBVA_F_ENABLE: VBVA_F_DISABLE;
213 pCtl->Enable.u32Offset = pCtx->offVRAMBuffer;
214 pCtl->Enable.i32Result = VERR_NOT_SUPPORTED;
215 pCtl->Enable.u32Flags |= VBVA_F_ABSOFFSET;
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/HpetTimerDxe/
H A DHpetTimer.c270 Enable or disable the main counter in the HPET Timer.
272 @param Enable If TRUE, then enable the main counter in the HPET Timer.
277 IN BOOLEAN Enable
280 mHpetGeneralConfiguration.Bits.MainCounterEnable = Enable ? 1 : 0;
363 // Enable the HPET counter once the new COMPARATOR value has been set.
577 // Enable HPET Timer interrupt generation
588 // Enable HPET MSI Interrupt
593 // Enable timer interrupt through I/O APIC
600 // Enable HPET Interrupt Generation
612 // Enable th
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