4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Public include file for I/O APIC library.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync I/O APIC library assumes I/O APIC is enabled. It does not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync handles cases where I/O APIC is disabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Read a 32-bit I/O APIC register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Index is >= 0x100, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Index Specifies the I/O APIC register to read.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The 32-bit value read from the I/O APIC register specified by Index.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Write a 32-bit I/O APIC register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Index is >= 0x100, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Index Specifies the I/O APIC register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value Specifies the value to write to the I/O APIC register specified by Index.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The 32-bit value written to I/O APIC register specified by Index.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Set the interrupt mask of an I/O APIC interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Irq Specifies the I/O APIC interrupt to enable or disable.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If FALSE, then disable the I/O APIC interrupt specified by Irq.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Configures an I/O APIC interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mode to the Local APIC of the currntly executing CPU. The default state of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync be used to enable(unmask) the I/O APIC Interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Vector >= 0x100, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If DeliveryMode is not supported, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Irq Specifies the I/O APIC interrupt to initialize.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector The 8-bit interrupt vector associated with the I/O APIC
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Interrupt. Must be in the range 0x10..0xFE.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync interrupt is handled. The only supported values are:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 0: IO_APIC_DELIVERY_MODE_FIXED
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 2: IO_APIC_DELIVERY_MODE_SMI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 4: IO_APIC_DELIVERY_MODE_NMI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 5: IO_APIC_DELIVERY_MODE_INIT
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 7: IO_APIC_DELIVERY_MODE_EXTINT
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param LevelTriggered TRUE specifies a level triggered interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FALSE specifies an edge triggered interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AssertionLevel TRUE specified an active high interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FALSE specifies an active low interrupt.