Searched refs:fence (Results 1 - 3 of 3) sorted by relevance

/solaris-x11-s12/open-src/kernel/i915/src/
H A Di915_gem.c53 struct drm_i915_fence_reg *fence,
63 /* As we do not have an associated fence register, we will force
1152 * object through the GTT and then lose the fence register due to
1195 /* Previous chips need a power-of-two fence region when tiling */
1212 * potential fence register mapping if needed.
1220 * if a fence register is needed for the object.
1228 * fence register that can contain the object.
1286 * a fence register, and mapping the appropriate aperture address into
1788 * attached to the fence, otherwise just clear the fence
2346 fence_number(struct drm_i915_private *dev_priv, struct drm_i915_fence_reg *fence) argument
2352 i915_gem_object_update_fence(struct drm_i915_gem_object *obj, struct drm_i915_fence_reg *fence, bool enable) argument
2392 struct drm_i915_fence_reg *fence; local
[all...]
H A Di915_irq.c1486 /* Simply ignore tiling or any overlapping fence.
1638 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1643 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1648 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1651 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
H A Di915_drv.h303 u64 fence[I915_MAX_NUM_FENCES]; member in struct:drm_i915_error_state
868 /** LRU list of objects with fence regs on them. */
1276 * Whether the tiling parameters for the currently associated fence
1280 * command (such as BLT on gen2/3), as a "fence".
1311 * Is the GPU currently using a fence to access this buffer,
1497 * rows, which changed the alignment requirements and fence programming.

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