Searched refs:post_qid (Results 1 - 12 of 12) sorted by relevance

/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-channel-fp.c49 channel->type, channel->post_qid,
81 "free_length %d", channel->type, channel->post_qid,
101 channel->type, channel->post_qid,
125 channel->post_qid, channel->compl_qid, offset,
132 channel->type, channel->post_qid, channel->compl_qid,
186 channel->type, channel->post_qid,
238 return channel->post_qid;
H A Dxgehal-channel.c96 __hal_channel_allocate(xge_hal_device_h devh, int post_qid, argument
105 xge_assert(post_qid + 1 >= XGE_HAL_MIN_FIFO_NUM &&
106 post_qid + 1 <= XGE_HAL_MAX_FIFO_NUM);
110 xge_assert(post_qid + 1 >= XGE_HAL_MIN_RING_NUM &&
111 post_qid + 1 <= XGE_HAL_MAX_RING_NUM);
133 channel->post_qid = post_qid;
317 tmp->post_qid == attr->post_qid &&
H A Dxgehal-ring.c253 queue = &ring->config->queue[attr->post_qid];
355 queue = &ring->config->queue[ring->channel.post_qid];
398 queue = &ring->config->queue[ring->channel.post_qid];
411 val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);
414 ring->channel.post_qid, (unsigned long long)val64);
417 ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
441 val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
456 ring->channel.post_qid, queue->buffer_mode);
473 &bar0->prc_ctrl_n[ring->channel.post_qid]);
476 val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
[all...]
H A Dxgehal-device-fp.c120 (fifo->channel.post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET));
371 hldev->irq_workload_rxd[channel->post_qid] += *got_rx;
372 hldev->irq_workload_rxcnt[channel->post_qid] ++;
374 hldev->irq_workload_rxlen[channel->post_qid] += got_bytes;
418 hldev->irq_workload_txd[channel->post_qid] += *got_tx;
419 hldev->irq_workload_txcnt[channel->post_qid] ++;
421 hldev->irq_workload_txlen[channel->post_qid] += got_bytes;
H A Dxgehal-fifo.c161 queue = &fifo->config->queue[attr->post_qid];
193 (attr->post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET));
473 tmp->post_qid == i) {
H A Dxgehal-ring-fp.c490 xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_pre_post: rxd 0x"XGE_OS_LLXFMT" posted %d post_qid %d",
493 ((xge_hal_ring_t *)channelh)->channel.post_qid);
724 "compl_index %d post_qid %d t_code %d rxd 0x"XGE_OS_LLXFMT,
726 ((xge_hal_channel_t*)ring)->post_qid, *t_code,
H A Dxgehal-mgmtaux.c959 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", channel->post_qid);
998 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", channel->post_qid);
1282 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", channel->post_qid);
1333 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", channel->post_qid);
H A Dxgehal-device.c6445 * @ring: The post_qid of the ring.
6471 * @ring: The post_qid of the FIFO.
6516 int ring = channel->post_qid;
6526 int fifo = channel->post_qid;
6663 int ring = channel->post_qid;
6670 hldev->config.ring.queue[channel->post_qid].intr_vector =
6673 int fifo = channel->post_qid;
6680 hldev->config.fifo.queue[channel->post_qid].intr_vector =
H A Dxgehal-mgmt.c548 __hal_update_ring_bump( (xge_hal_device_t *) channel->devh, channel->post_qid, channel_info);
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-channel.h226 * @post_qid: Queue ID to post descriptors. For the link layer this
254 int post_qid; member in struct:xge_hal_channel_attr_t
325 * @post_qid: Identifies Xframe queue used for posting descriptors.
390 int post_qid; member in struct:__anon6597
426 __hal_channel_allocate(xge_hal_device_h devh, int post_qid,
/illumos-gate/usr/src/uts/common/io/xge/drv/
H A Dxge.c906 i = channel->post_qid;
935 assigned[i]->post_qid, i);
942 assigned[i]->post_qid, i);
H A Dxgell.c977 ((xge_hal_channel_t *)ring->channelh)->post_qid,
990 ring->channelh)->post_qid);
997 ring->channelh)->post_qid);
1604 attr.post_qid = rx_ring->index;
1760 attr.post_qid = tx_ring->index;

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