Searched defs:clock (Results 1 - 11 of 11) sorted by relevance

/solaris-x11-s12/open-src/kernel/i915/src/
H A Dintel_ddi.c433 static unsigned wrpll_get_budget_for_freq(int clock) argument
437 switch (clock) {
522 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
567 intel_ddi_calculate_wrpll(int clock /* in Hz */,
575 freq2k = clock / 100;
577 budget = wrpll_get_budget_for_freq(clock);
579 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
631 clock, *p_out, *n2_out, *r2_out);
644 int clock = intel_crtc->config.port_clock; local
695 intel_ddi_calculate_wrpll(clock * 100
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H A Di915_gem_debug.c463 print_clock(char *name, int clock) { argument
464 if (clock == -1)
465 DRM_ERROR("%s clock: unknown", name);
467 DRM_ERROR("%s clock: %d Mhz", name, clock);
H A Dintel_dp.c105 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 int target_clock = mode->clock;
142 target_clock = fixed_mode->clock;
154 if (mode->clock < 10000)
307 /* The clock divider is based off the hrawclk,
312 * clock divider.
321 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
323 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
690 int lane_count, clock; local
717 "max bw %02x pixel clock
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H A Dintel_tv.c359 int clock; member in struct:tv_mode
412 * The constants below were all computed using a 107.520MHz clock
424 .clock = 108000,
451 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
467 .clock = 108000,
493 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
509 .clock = 108000,
536 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
552 .clock = 108000,
579 /* desired 3.5800000 actual 3.5800000 clock 107.5
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H A Dintel_sdvo.c89 /* Pixel clock limitations reported by the SDVO device, in kHz */
582 if (mode->clock >= 100000)
584 else if (mode->clock >= 50000)
745 uint16_t clock,
752 args.clock = clock;
802 mode_clock = mode->clock;
804 dtd->part1.clock = (u16) mode_clock;
860 mode->clock = dtd->part1.clock * 1
744 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, uint16_t clock, uint16_t width, uint16_t height) argument
1057 struct dpll *clock = &pipe_config->dpll; local
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H A Dintel_bios.h354 u16 clock; /**< In 10khz */ member in struct:lvds_dvo_timing
H A Dintel_pm.c55 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
1030 * @clock_in_khz: pixel clock
1040 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1055 * Note: we need to make sure we don't overflow for various clock &
1111 int clock = crtc->mode.clock; local
1115 wm = intel_calculate_wm(clock, &pineview_display_wm,
1125 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1134 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1143 wm = intel_calculate_wm(clock,
1172 int htotal, hdisplay, clock, pixel_size; local
1256 int hdisplay, htotal, pixel_size, clock; local
1302 int clock, pixel_size; local
1494 int clock = crtc->mode.clock; local
1613 int clock = enabled->mode.clock; local
1751 int hdisplay, htotal, pixel_size, clock; local
2662 int clock; local
2695 int clock; local
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H A Dintel_sdvo_regs.h81 u16 clock; /**< pixel clock, in 10kHz units */ member in struct:intel_sdvo_dtd::__anon129
111 u16 min; /**< pixel clock, in 10kHz units */
112 u16 max; /**< pixel clock, in 10kHz units */
118 u16 clock; member in struct:intel_sdvo_preferred_input_timing_args
H A Dintel_display.c60 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
222 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 static void pineview_clock(int refclk, intel_clock_t *clock) argument
414 clock->m = clock->m2 + 2;
415 clock->p = clock->p1 * clock->p2;
416 clock->vco = refclk * clock
425 i9xx_clock(int refclk, intel_clock_t *clock) argument
454 intel_PLL_is_valid(struct drm_device *dev, const intel_limit_t *limit, const intel_clock_t *clock) argument
489 intel_clock_t clock; local
550 intel_clock_t clock; local
609 intel_clock_t clock; local
4534 struct dpll *clock = &crtc->config.dpll; local
4633 struct dpll *clock = &crtc->config.dpll; local
4858 intel_clock_t clock, reduced_clock; local
5503 ironlake_compute_clocks(struct drm_crtc *crtc, intel_clock_t *clock, bool *has_reduced_clock, intel_clock_t *reduced_clock) argument
5708 intel_clock_t clock, reduced_clock; local
6951 intel_clock_t clock; local
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/solaris-x11-s12/open-src/kernel/drm/src/
H A Ddrm_edid.c56 /* Reported 135MHz pixel clock is too high, needs adjustment */
1661 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1773 if (mode->clock > max_clock)
2246 * Calculate the alternate clock for the CEA mode
2252 unsigned int clock = cea_mode->clock; local
2255 return clock;
2263 clock = clock * 1001 / 1000;
2265 clock
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/solaris-x11-s12/open-src/kernel/sys/drm/
H A Ddrm_crtc.h92 MODE_NOCLOCK, /* no fixed clock available */
93 MODE_CLOCK_HIGH, /* clock required is too high */
94 MODE_CLOCK_LOW, /* clock required is too low */
95 MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */
122 .name = nm, .status = 0, .type = (t), .clock = (c), \
142 int clock; /* in kHz */ member in struct:drm_display_mode
577 * @max_tmds_clock: max clock rate, if found

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