Cross Reference: /solaris-x11-s12/open-src/kernel/i915/src/intel

Lines Matching defs:clock
55 	return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
1030  * @clock_in_khz: pixel clock
1040  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1055 	 * Note: we need to make sure we don't overflow for various clock &
1111 		int clock = crtc->mode.clock;
1115 		wm = intel_calculate_wm(clock, &pineview_display_wm,
1125 		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1134 		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1143 		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1172 	int htotal, hdisplay, clock, pixel_size;
1185 	clock = crtc->mode.clock;
1189 	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1199 	line_time_us = ((htotal * 1000) / clock);
1256 	int hdisplay, htotal, pixel_size, clock;
1270 	clock = crtc->mode.clock;
1273 	line_time_us = (htotal * 1000) / clock;
1278 	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1302 	int clock, pixel_size;
1309 	clock = crtc->mode.clock;	/* VESA DOT Clock */
1312 	entries = (clock / 1000) * pixel_size;
1315 	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1318 	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
1321 	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1494 		int clock = crtc->mode.clock;
1501 		line_time_us = ((htotal * 1000) / clock);
1572 		planea_wm = intel_calculate_wm(crtc->mode.clock,
1586 		planeb_wm = intel_calculate_wm(crtc->mode.clock,
1613 		int clock = enabled->mode.clock;
1620 		line_time_us = (htotal * 1000) / clock;
1675 	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1751 	int hdisplay, htotal, pixel_size, clock;
1764 	clock = crtc->mode.clock;
1767 	line_time_us = (htotal * 1000) / clock;
1772 	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2107 	pixel_rate = intel_crtc->config.adjusted_mode.clock;
2348 	 * row at the given clock rate, multiplied by 8.
2350 	linetime = POS_DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2662 	int clock;
2671 	clock = crtc->mode.clock;
2674 	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2695 	int clock;
2706 	clock = crtc->mode.clock;
2707 	if (!clock) {
2712 	line_time_us = (sprite_width * 1000) / clock;
2722 	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2841  * and include an extra 2 entries to account for clock crossings.
3045 	 * the hw runs at the minimal clock before selecting the desired
3407 			 * clock domain, so in order to boost the bandwidth
3916 	 * On Ibex Peak and Cougar Point, we need to disable clock
4011 	 * On Ibex Peak and Cougar Point, we need to disable clock
4084 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4288 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4379 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4416 	/* Conservative clock gating settings for now */