Searched refs:pVMRC (Results 1 - 25 of 25) sorted by relevance

/vbox/src/VBox/VMM/VMMRC/
H A DPDMRCDevice.cpp118 PVM pVM = pDevIns->Internal.s.pVMRC;
172 PVM pVM = pDevIns->Internal.s.pVMRC;
203 int rc = PGMPhysRead(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbRead);
218 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbWrite);
232 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu0(pDevIns->Internal.s.pVMRC));
244 VMSTATE enmVMState = pDevIns->Internal.s.pVMRC->enmVMState;
257 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
267 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
278 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
288 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlag
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/vbox/src/VBox/VMM/VMMR3/
H A DVMMTests.cpp90 rc = VMMR3CallRC(pVM, RCPtrEP, 4, pVM->pVMRC, uMsr, cBatch, RCPtrResults);
208 CPUMPushHyper(pVCpu, pVM->pVMRC);
263 CPUMPushHyper(pVCpu, pVM->pVMRC);
507 CPUMPushHyper(pVCpu, pVM->pVMRC);
569 CPUMPushHyper(pVCpu, pVM->pVMRC);
710 CPUMPushHyper(pVCpu, pVM->pVMRC);
881 rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
891 rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
899 rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
916 rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMs
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H A DPDMQueue.cpp91 pQueue->pVMRC = fRZEnabled ? pVM->pVMRC : NIL_RTRCPTR;
458 if (pQueue->pVMRC)
460 pQueue->pVMRC = NIL_RTRCPTR;
593 if (pQueue->pVMRC)
595 pQueue->pVMRC = pVM->pVMRC;
848 if (pQueue->pVMRC)
H A DPDMCritSect.cpp75 pCur->pVMRC = pVM->pVMRC;
80 pCur->pVMRC = pVM->pVMRC;
181 pCritSect->pVMRC = pVM->pVMRC;
278 pCritSect->pVMRC = pVM->pVMRC;
526 pCritSect->pVMRC = NIL_RTRCPTR;
596 pCritSect->pVMRC
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H A DMMHyper.cpp156 pVM->pVMRC = (RTRCPTR)GCPtr;
158 pVM->aCpus[i].pVMRC = pVM->pVMRC;
364 pVM->pVMRC += offDelta;
366 pVM->aCpus[i].pVMRC = pVM->pVMRC;
372 pVM->mm.s.pHyperHeapR3->pVMRC = pVM->pVMRC;
841 pHeap->pVMRC = pVM->pVMRC;
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H A DPGMPool.cpp244 pPool->pVMRC = pVM->pVMRC;
410 pVM->pgm.s.pPoolR3->pVMRC = pVM->pVMRC;
H A DPATMSSM.cpp1266 LogFlow(("Changing fLocalForcedActions fixup from %RRv to %RRv\n", uFixup, pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions)));
1267 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
1314 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
1359 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
H A DPDMDevice.cpp328 pDevIns->Internal.s.pVMRC = pVM->pVMRC;
H A DPDM.cpp546 pDevIns->Internal.s.pVMRC = pVM->pVMRC;
567 pDrvIns->Internal.s.pVMRC = pVM->pVMRC;
H A DPDMDriver.cpp699 pNew->Internal.s.pVMRC = pDrv->pReg->fFlags & PDM_DRVREG_FLAGS_RC ? pVM->pVMRC : NIL_RTRCPTR;
H A DTM.cpp1083 * Iterate the timers updating the pVMRC pointers.
1087 pTimer->pVMRC = pVM->pVMRC;
1406 pTimer->pVMRC = pVM->pVMRC;
H A DPDMLdr.cpp352 *pValue = pVM->pVMRC;
H A DPATMPatch.cpp364 dest = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
H A DVMM.cpp587 CPUMPushHyper(pVCpu, pVM->pVMRC); /* Param 0: pVM */
/vbox/src/VBox/VMM/VMMRZ/
H A DVMMRZ.cpp141 pVCpu->pVMRC->vmm.s.fRCLoggerFlushingDisabled = true;
173 pVCpu->pVMRC->vmm.s.fRCLoggerFlushingDisabled = false;
/vbox/include/VBox/vmm/
H A Dvmapi.h50 # define VM_RC_ADDR(pVM, pvInVM) ( (RTRCPTR)((RTRCUINTPTR)pVM->pVMRC + (uint32_t)((uintptr_t)(pvInVM) - (uintptr_t)pVM->pVMR3)) )
52 # define VM_RC_ADDR(pVM, pvInVM) ( (RTRCPTR)((RTRCUINTPTR)pVM->pVMRC + (uint32_t)((uintptr_t)(pvInVM) - (uintptr_t)pVM->pVMR0)) )
66 # define VM_R3_ADDR(pVM, pvInVM) ( (RTR3PTR)((RTR3UINTPTR)pVM->pVMR3 + (uint32_t)((uintptr_t)(pvInVM) - (uintptr_t)pVM->pVMRC)) )
83 # define VM_R0_ADDR(pVM, pvInVM) ( (RTR0PTR)((RTR0UINTPTR)pVM->pVMR0 + (uint32_t)((uintptr_t)(pvInVM) - (uintptr_t)pVM->pVMRC)) )
H A Dvm.h108 PVMRC pVMRC; /* 32 / 20 */ member in struct:VMCPU
848 RCPTRTYPE(struct VM *) pVMRC; member in struct:VM
/vbox/src/VBox/HostDrivers/Support/testcase/
H A DtstInt.cpp94 pVM->pVMRC = 0;
/vbox/src/VBox/VMM/VMMAll/
H A DPDMAllQueue.cpp168 Assert(pQueue->pVMR3 && pQueue->pVMRC);
H A DEMAll.cpp378 rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
382 rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
/vbox/src/VBox/VMM/include/
H A DPDMInternal.h156 PVMRC pVMRC; member in struct:PDMDEVINSINT
249 PVMRC pVMRC; member in struct:PDMDRVINSINT
279 * This chain is used for relocating pVMRC and device cleanup. */
290 PVMRC pVMRC; member in struct:PDMCRITSECTINT
332 * This chain is used for relocating pVMRC and device cleanup. */
343 PVMRC pVMRC; member in struct:PDMCRITSECTRWINT
866 PVMRC pVMRC; member in struct:PDMQUEUE
H A DMMInternal.h354 PVMRC pVMRC; member in struct:MMHYPERHEAP
H A DTMInternal.h187 PVMRC pVMRC; member in struct:TMTIMER
H A DPGMInternal.h2271 PVMRC pVMRC; member in struct:PGMPOOL
/vbox/src/VBox/VMM/testcase/
H A DtstVMStruct.h369 GEN_CHECK_OFF(MMHYPERHEAP, pVMRC);
474 GEN_CHECK_OFF(PDMDEVINSINT, pVMRC);
506 GEN_CHECK_OFF(PDMDRVINSINT, pVMRC);
532 GEN_CHECK_OFF(PDMCRITSECTINT, pVMRC);
544 GEN_CHECK_OFF(PDMCRITSECTRWINT, pVMRC);
562 GEN_CHECK_OFF(PDMQUEUE, pVMRC);
880 GEN_CHECK_OFF(PGMPOOL, pVMRC);
1094 GEN_CHECK_OFF(TMTIMER, pVMRC);
1327 GEN_CHECK_OFF(VM, pVMRC);
1390 GEN_CHECK_OFF(VMCPU, pVMRC);
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