Searched refs:Pte (Results 1 - 9 of 9) sorted by relevance

/vbox/src/VBox/VMM/VMMAll/
H A DPGMAllShw.h69 # define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present )
70 # define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
71 # define SHW_PTE_IS_US(Pte) ( (Pte).n.u1User )
72 # define SHW_PTE_IS_A(Pte) ( (Pte).n.u1Accessed )
73 # define SHW_PTE_IS_D(Pte) ( (Pte)
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H A DPGMAllGst.h206 GSTPTE register Pte; local
209 pWalk->Pte.u = Pte.u = pPte->u;
210 if (!Pte.n.u1Present)
212 if (RT_UNLIKELY(!GST_IS_PTE_VALID(pVCpu, Pte)))
218 pWalk->Core.GCPhys = GST_GET_PDE_GCPHYS(Pte)
220 uint8_t fEffectiveXX = (uint8_t)pWalk->Pte.u
230 pWalk->Core.fEffectiveNX = ( pWalk->Pte.n.u1NoExecute
291 *pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK | X86_PTE_RW | X86_PTE_US)) /* NX not needed */
357 GSTPTE Pte local
515 GSTPTE Pte = pPT->a[iPTE]; local
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H A DPGMAllMap.cpp77 X86PTEPAE Pte; local
78 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
90 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
93 PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
100 Pte.u += PAGE_SIZE;
H A DPGMAllPool.cpp3207 X86PTE Pte;
3210 Pte.u = (pPT->a[iPte].u & u32AndMask) | u32OrMask;
3211 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3212 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3214 ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3282 X86PTEPAE Pte;
3285 Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) | u64OrMask;
3286 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3287 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3289 PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte
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H A DPGMAllBth.h478 /*AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto */
524 if (!GstWalk.Pte.n.u1Dirty)
529 GstWalk.Pte.u |= X86_PTE_A | X86_PTE_D;
534 GstWalk.Pte.u |= X86_PTE_A;
537 Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540 ("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
635 //AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
1843 Log2(("SyncPageWorker: invalid address in Pte\
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/vbox/src/VBox/VMM/include/
H A DPGMGstDefs.h109 # define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PTE_PG_MASK))
112 # define GST_GET_PTE_SHW_FLAGS(pVCpu, Pte) ((Pte).u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G)) /**< @todo Could return P|RW|US|A|D here without consulting the PTE. */
116 # define GST_IS_PTE_VALID(pVCpu, Pte) (true)
140 # define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PDE_PG_MASK))
152 # define GST_GET_PTE_SHW_FLAGS(pVCpu, Pte) ((Pte).u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G))
156 # define GST_IS_PTE_VALID(pVCpu, Pte) (tru
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H A DPGMInternal.h447 # define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
448 # define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
449 # define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
450 # define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
451 # define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte)
2692 X86PTEPAE Pte; member in struct:PGMPTWALKGSTAMD64
2717 X86PTEPAE Pte; member in struct:PGMPTWALKGSTPAE
2738 X86PTE Pte; member in struct:PGMPTWALKGST32BIT
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/vbox/src/VBox/VMM/VMMR3/
H A DPGMDbg.cpp1154 X86PTEPAE Pte;
1155 Pte.u = PGMSHWPTEPAE_GET_U(pPT->a[i]);
1161 Pte.n.u1Write ? 'W' : 'R',
1162 Pte.n.u1User ? 'U' : 'S',
1163 Pte.n.u1Accessed ? 'A' : '-',
1164 Pte.n.u1Dirty ? 'D' : '-',
1165 Pte.n.u1Global ? 'G' : '-',
1166 Pte.n.u1WriteThru ? "WT" : "--",
1167 Pte.n.u1CacheDisable? "CD" : "--",
1168 Pte
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/vbox/src/VBox/Debugger/
H A DDBGCEmulateCodeView.cpp3055 X86PTEPAE Pte; local
3056 Pte.u = 0;
3057 rc = pCmdHlp->pfnMemRead(pCmdHlp, &Pte, cbEntry, &VarPTEAddr, NULL);
3073 Pte.u,
3074 Pte.u & X86_PTE_PAE_PG_MASK,
3075 Pte.n.u1Present ? "p " : "np",
3076 Pte.n.u1Write ? "w" : "r",
3077 Pte.n.u1User ? "u" : "s",
3078 Pte.n.u1Accessed ? "a " : "na",
3079 Pte
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