Searched refs:Int (Results 1 - 22 of 22) sorted by relevance

/vbox/src/VBox/VMM/testcase/
H A DtstMicroRC.cpp76 pTst->aIDT[iIDT].Int.u16OffsetHigh = uHandler >> 16;
77 pTst->aIDT[iIDT].Int.u16OffsetLow = uHandler & 0xffff;
78 pTst->aIDT[iIDT].Int.u16SegSel = SELMGetHyperCS(&g_VM);
79 pTst->aIDT[iIDT].Int.u2DPL = 3;
80 pTst->aIDT[iIDT].Int.u1Present = 1;
81 pTst->aIDT[iIDT].Int.u1Fixed0 = 0;
82 pTst->aIDT[iIDT].Int.u1Fixed1 = 0;
83 pTst->aIDT[iIDT].Int.u1Fixed2 = 0;
84 pTst->aIDT[iIDT].Int.u1Fixed3 = 0;
85 pTst->aIDT[iIDT].Int
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H A DtstVMStruct.h557 GEN_CHECK_OFF_DOT(PDMQUEUE, u.Int.pfnCallback);
/vbox/src/VBox/Devices/Bus/
H A DMsixCommon.cpp44 return PCIDevGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL);
64 return (uint8_t*)pDev->Int.s.CTX_SUFF(pMsixPage) + off;
146 msixCheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
205 pDev->Int.s.u8MsixCapOffset = iCapOffset;
206 pDev->Int.s.u8MsixCapSize = VBOX_MSIX_CAP_SIZE;
209 pDev->Int.s.pMsixPageR3 = NULL;
211 rc = MMHyperAlloc(pVM, 0x1000, 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->Int.s.pMsixPageR3);
212 if (RT_FAILURE(rc) || (pDev->Int.s.pMsixPageR3 == NULL))
214 RT_BZERO(pDev->Int.s.pMsixPageR3, 0x1000);
215 pDev->Int
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H A DMsiCommon.cpp30 return PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL);
41 iOff += pDev->Int.s.u8MsiCapOffset;
48 iOff += pDev->Int.s.u8MsiCapOffset;
66 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
67 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
72 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
79 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
108 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
109 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
192 int32_t iOff = u32Address - pDev->Int
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H A DDevPciIch9.cpp227 pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
326 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
327 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
341 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
439 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
440 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
457 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
594 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
637 if (pPciDev->Int.s.uIrqPinState != iLevel)
639 pPciDev->Int
[all...]
H A DDevPCI.cpp247 PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
254 r = &d->Int.s.aIORegions[i];
374 r = &d->Int.s.aIORegions[reg];
507 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
508 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
522 pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
553 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
554 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
568 *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
626 pPciDev->Int
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/vbox/include/VBox/
H A Dpci.h533 } Int; member in struct:PCIDevice
951 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
956 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
961 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
966 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
971 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
976 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
981 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
986 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
991 pDev->Int
[all...]
H A Dtypes.h562 VBOXIDTE_INTERRUPTGATE Int; member in union:VBOXIDTE
711 VBOXIDTE64_INTERRUPTGATE Int; member in union:VBOXIDTE64
/vbox/include/VBox/vmm/
H A Dpdmthread.h256 } Int; member in union:PDMTHREAD::__anon364
/vbox/src/VBox/Devices/testcase/
H A DtstDeviceStructSize.cpp271 CHECK_MEMBER_ALIGNMENT(PCIDEVICE, Int.s, 16);
272 CHECK_MEMBER_ALIGNMENT(PCIDEVICE, Int.s.aIORegions, 16);
H A DtstDeviceStructSizeRC.cpp145 GEN_CHECK_OFF(PCIDEVICE, Int);
146 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions);
147 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[1]);
148 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[PCI_NUM_REGIONS - 1]);
149 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[0].addr);
150 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[0].size);
151 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[0].type);
152 GEN_CHECK_OFF(PCIDEVICE, Int.s.aIORegions[0].padding);
153 GEN_CHECK_OFF(PCIDEVICE, Int.s.pBusR3);
154 GEN_CHECK_OFF(PCIDEVICE, Int
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/vbox/src/VBox/VMM/include/
H A DDBGFInternal.h143 } Int; member in union:DBGFINFO::__anon16879
H A DPDMBlkCacheInternal.h237 } Int; member in union:PDMBLKCACHE::__anon16946
H A DPDMInternal.h837 } Int; member in union:PDMQUEUE::__anon16953
/vbox/src/VBox/VMM/VMMR3/
H A DDBGFInfo.cpp399 pInfo->u.Int.pfnHandler = pfnHandler;
734 rc = VMR3ReqCallVoidWaitU(pUVM, idCpu, (PFNRT)Info.u.Int.pfnHandler, 3, pUVM->pVM, pHlp, pszArgs);
736 Info.u.Int.pfnHandler(pUVM->pVM, pHlp, pszArgs);
899 rc = VMR3ReqCallVoidWaitU(pUVM, VMCPUID_ANY, (PFNRT)pInfo->u.Int.pfnHandler, 3, pVM, pHlp, pszArgs);
901 pInfo->u.Int.pfnHandler(pVM, pHlp, pszArgs);
H A DPDMThread.cpp79 rc = pThread->u.Int.pfnWakeUp(pThread->Internal.s.pVM, pThread);
316 pThread->u.Int.pfnThread = pfnThread;
317 pThread->u.Int.pfnWakeUp = pfnWakeUp;
791 rc = pThread->u.Int.pfnThread(pThread->Internal.s.pVM, pThread);
H A DPDMAsyncCompletion.cpp104 } Int; member in union:PDMASYNCCOMPLETIONTEMPLATE::__anon16853
366 pTemplate->u.Int.pvUser = pvUser2;
367 pTemplate->u.Int.pfnCompleted = pfnCompleted;
802 pTemplate->u.Int.pfnCompleted(pTemplate->pVM, pTask->pvUser, pTemplate->u.Int.pvUser, rc);
H A DPDMBlkCache.cpp518 rc = pBlkCache->u.Int.pfnXferEnqueue(pBlkCache->u.Int.pvUser,
1356 pBlkCache->u.Int.pfnXferComplete = pfnXferComplete;
1357 pBlkCache->u.Int.pfnXferEnqueue = pfnXferEnqueue;
1358 pBlkCache->u.Int.pfnXferEnqueueDiscard = pfnXferEnqueueDiscard;
1359 pBlkCache->u.Int.pvUser = pvUser;
1892 pBlkCache->u.Int.pfnXferComplete(pBlkCache->u.Int.pvUser,
H A DPDMQueue.cpp323 pQueue->u.Int.pfnCallback = pfnCallback;
764 if (!pQueue->u.Int.pfnCallback(pQueue->pVMR3, pItems))
/vbox/
H A Dconfigure.vbs1505 iMajor = Int(Left(strVer, 1)) ' Is Int() the right thing here? I want atoi()!!!
1506 iMinor = Int(Mid(strVer, 3, 1))
1507 iPatch = Int(Mid(strVer, 5))
1633 iMajor = Int(Left(strVer, 1)) ' Is Int() the right thing here? I want atoi()!!!
1634 iMinor = Int(Mid(strVer, 3, 1))
1635 iPatch = Int(Mid(strVer, 5))
/vbox/src/VBox/Devices/PC/BIOS/
H A Dorgs.asm682 ; b3: 1=wait for extern event supported (Int 15h/41h)
/vbox/src/VBox/Devices/USB/
H A DDevOHCI.cpp3540 RTStrPrintf(sz, sizeof(sz), "Int%02x before", iList);
3599 RTStrPrintf(sz, sizeof(sz), "Int%02x after ", iList);
5397 SSMFIELD_ENTRY_OLD( PciDev.Int, 224),

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