Cross Reference: /vbox/src/VBox/Devices/Bus/DevPCI.cpp

Lines Matching refs:Int
247     PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
254         r = &d->Int.s.aIORegions[i];
374         r = &d->Int.s.aIORegions[reg];
507                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
508                 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
522             pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
553                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
554                 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
568             *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
626             pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
670     if (pPciDev->Int.s.uIrqPinState != iLevel)
672         pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
703             if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
705             else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
715                     pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
1228             int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1416                 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1468             pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1509         DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1521             rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1547         pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1724     pPciDev->Int.s.pBusR3           = pBus;
1725     pPciDev->Int.s.pBusR0           = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1726     pPciDev->Int.s.pBusRC           = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1727     pPciDev->Int.s.pfnConfigRead    = pci_default_read_config;
1728     pPciDev->Int.s.pfnConfigWrite   = pci_default_write_config;
1733         AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1800     PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1826         *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1827     pPciDev->Int.s.pfnConfigRead  = pfnRead;
1830         *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1831     pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1968                     PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2076             pBus->devices[i]->Int.s.pBusRC += offDelta;
2331         pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2356             AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2357             pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2367             pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2389             AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2390             u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2399             u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2481             pBus->devices[i]->Int.s.pBusRC += offDelta;
2569     pBus->PciDev.Int.s.pfnBridgeConfigRead  = pcibridgeR3ConfigRead;
2570     pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;