Lines Matching refs:Int
227 pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
326 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
327 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
341 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
439 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
440 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
457 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
594 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
637 if (pPciDev->Int.s.uIrqPinState != iLevel)
639 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
790 return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
818 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
820 PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
859 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
971 rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
1029 Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1034 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1046 pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
1062 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1063 pPciDev->Int.s.pfnConfigRead = pfnRead;
1066 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1067 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1086 int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1091 rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1096 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1099 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1104 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1107 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1111 if (pDev->Int.s.u8MsixCapOffset != 0)
1113 Assert(pDev->Int.s.pMsixPageR3 != NULL);
1114 SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1163 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1164 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1174 pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1192 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1193 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1204 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1362 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1415 pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1460 DevTmp.Int.s.fFlags = 0;
1461 DevTmp.Int.s.u8MsiCapOffset = 0;
1462 DevTmp.Int.s.u8MsiCapSize = 0;
1463 DevTmp.Int.s.u8MsixCapOffset = 0;
1464 DevTmp.Int.s.u8MsixCapSize = 0;
1465 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1468 SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1469 SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1470 SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1471 SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1472 SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1473 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1478 if (DevTmp.Int.s.u8MsixCapOffset != 0)
1513 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1514 pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1515 pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1516 pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1517 pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1518 if (DevTmp.Int.s.u8MsixCapSize != 0)
1520 Assert(pDev->Int.s.pMsixPageR3 != NULL);
1521 memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1862 pBus = pBus->aPciDev.Int.s.pBusR3;
1960 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
1961 && (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1964 return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1968 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
1969 && (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1972 return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1994 PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2058 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
2059 && (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2062 MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2063 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2069 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
2070 && (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2073 MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2074 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2317 pPciDev->Int.s.pBusR3 = pBus;
2318 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2319 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2320 pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2321 pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2326 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2388 PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2679 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2712 pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2719 pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2753 pDev->Int.s.pBusRC += offDelta;
2754 if (pDev->Int.s.pMsixPageRC)
2755 pDev->Int.s.pMsixPageRC += offDelta;
2866 pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2867 pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;