/vbox/src/VBox/Devices/EFI/Firmware/NetworkPkg/Application/IpsecConfig/ |
H A D | PolicyEntryOperation.h | 19 #define LOCAL BIT(0) 20 #define REMOTE BIT(1) 21 #define PROTO BIT(2) 22 #define LOCAL_PORT BIT(3) 23 #define REMOTE_PORT BIT(4) 24 #define ICMP_TYPE BIT(5) 25 #define ICMP_CODE BIT(6) 26 #define NAME BIT(7) 27 #define PACKET_FLAG BIT(8) 28 #define ACTION BIT( [all...] |
H A D | IpSecConfig.c | 241 { L"-enable", BIT(1)|BIT(0), BIT(1), BIT(2)|BIT(1)|BIT(0), 0 }, 242 { L"-disable", BIT(1)|BIT(0), BIT(1), BIT( [all...] |
H A D | IpSecConfig.h | 33 #define BIT(x) (UINT32) (1 << (x)) macro
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/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Universal/Network/UefiPxeBcDxe/ |
H A D | PxeBcDhcp.h | 122 #define BIT(x) (1 << x) macro 128 #define MTFTP_VENDOR_OPTION_BIT_MAP (BIT (PXEBC_VENDOR_TAG_MTFTP_IP) | \ 129 BIT (PXEBC_VENDOR_TAG_MTFTP_CPORT) | \ 130 BIT (PXEBC_VENDOR_TAG_MTFTP_SPORT) | \ 131 BIT (PXEBC_VENDOR_TAG_MTFTP_TIMEOUT) | \ 132 BIT (PXEBC_VENDOR_TAG_MTFTP_DELAY)) 136 #define DISCOVER_VENDOR_OPTION_BIT_MAP (BIT (PXEBC_VENDOR_TAG_DISCOVER_CTRL) | \ 137 BIT (PXEBC_VENDOR_TAG_DISCOVER_MCAST) | \ 138 BIT (PXEBC_VENDOR_TAG_BOOT_SERVERS) | \ 139 BIT (PXEBC_VENDOR_TAG_BOOT_MEN [all...] |
/vbox/src/VBox/Devices/EFI/Firmware/NetworkPkg/UefiPxeBcDxe/ |
H A D | PxeBcDhcp4.h | 128 #define BIT(x) (1 << x) macro 136 (BIT (PXEBC_VENDOR_TAG_MTFTP_IP) | \ 137 BIT (PXEBC_VENDOR_TAG_MTFTP_CPORT) | \ 138 BIT (PXEBC_VENDOR_TAG_MTFTP_SPORT) | \ 139 BIT (PXEBC_VENDOR_TAG_MTFTP_TIMEOUT) | \ 140 BIT (PXEBC_VENDOR_TAG_MTFTP_DELAY)) 143 (BIT (PXEBC_VENDOR_TAG_DISCOVER_CTRL) | \ 144 BIT (PXEBC_VENDOR_TAG_DISCOVER_MCAST) | \ 145 BIT (PXEBC_VENDOR_TAG_BOOT_SERVERS) | \ 146 BIT (PXEBC_VENDOR_TAG_BOOT_MEN [all...] |
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath9k/ |
H A D | ath9k.h | 92 BUF_AMPDU = BIT(0), 93 BUF_AGGR = BIT(1), 94 BUF_XRETRY = BIT(2), 259 #define AGGR_CLEANUP BIT(1) 260 #define AGGR_ADDBA_COMPLETE BIT(2) 261 #define AGGR_ADDBA_PROGRESS BIT(3) 360 #define SC_OP_INVALID BIT(0) 361 #define SC_OP_BEACONS BIT(1) 362 #define SC_OP_RXAGGR BIT(2) 363 #define SC_OP_TXAGGR BIT( [all...] |
H A D | hw.h | 179 ATH9K_HW_CAP_HT = BIT(0), 180 ATH9K_HW_CAP_RFSILENT = BIT(1), 181 ATH9K_HW_CAP_CST = BIT(2), 182 ATH9K_HW_CAP_AUTOSLEEP = BIT(4), 183 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), 184 ATH9K_HW_CAP_EDMA = BIT(6), 185 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), 186 ATH9K_HW_CAP_LDPC = BIT(8), 187 ATH9K_HW_CAP_FASTCLOCK = BIT(9), 188 ATH9K_HW_CAP_SGI_20 = BIT(1 [all...] |
H A D | eeprom.h | 214 #define LNA_CTL_BUF_MODE BIT(0) 215 #define LNA_CTL_ISEL_LO BIT(1) 216 #define LNA_CTL_ISEL_HI BIT(2) 217 #define LNA_CTL_BUF_IN BIT(3) 218 #define LNA_CTL_FEM_BAND BIT(4) 219 #define LNA_CTL_LOCAL_BIAS BIT(5) 220 #define LNA_CTL_FORCE_XPA BIT(6) 221 #define LNA_CTL_USE_ANT1 BIT(7)
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H A D | ath9k_eeprom_4k.c | 1018 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25); 1025 mask = BIT(0)|BIT(5)|BIT(15); 1030 mask = BIT( [all...] |
H A D | ath9k_ar9002_calib.c | 27 ADC_GAIN_CAL = BIT(0), 28 ADC_DC_CAL = BIT(1), 29 IQ_MISMATCH_CAL = BIT(2),
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H A D | ath9k_ar9003_calib.c | 37 IQ_MISMATCH_CAL = BIT(0), 38 TEMP_COMP_CAL = BIT(1), 191 if (ah->txchainmask & BIT(i)) {
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H A D | ath9k_ar9003_eeprom.c | 3043 return !!(pBase->featureEnable & BIT(5)); 3520 if ((ah->rxchainmask & BIT(chain)) || 3521 (ah->txchainmask & BIT(chain))) { 3683 if (ah->txchainmask & BIT(i)) { 4312 if (ah->caps.tx_chainmask & BIT(1)) 4316 if (ah->caps.tx_chainmask & BIT(2)) 4325 if (ah->caps.tx_chainmask & BIT(1)) 4329 if (ah->caps.tx_chainmask & BIT(2))
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H A D | ath9k_hw.c | 1185 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1739 if (tx_chainmask & BIT(0)) 1741 if (rx_chainmask & BIT(0))
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H A D | ath9k_ar9003_phy.c | 1061 if (ah->rxchainmask & BIT(i)) {
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/vbox/src/VBox/Devices/EFI/Firmware/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/ |
H A D | PrintInfo.c | 25 #define BIT(value, bit) ((value) & ((UINT64) 1) << (bit)) macro 946 if (BIT (Chara, 0) != 0) { 950 if (BIT (Chara, 1) != 0) { 954 if (BIT (Chara, 2) != 0) { 958 if (BIT (Chara, 3) != 0) { 962 if (BIT (Chara, 4) != 0) { 966 if (BIT (Chara, 5) != 0) { 970 if (BIT (Chara, 6) != 0) { 974 if (BIT (Chara, 7) != 0) { 978 if (BIT (Char [all...] |
H A D | QueryTable.c | 3006 #define BIT(Value, bit) ((Value) & ((UINT32) 1) << (bit)) macro 3010 #define CLR_BIT(Value, bit) ((Value) -= (BIT (Value, bit))) 3022 if (BIT (Value, Table[Index].Key) != 0) { 3108 if (BIT (Type, 7) != 0) {
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/vxge/ |
H A D | vxge_reg.h | 923 #define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3) 3465 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) 3642 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3) 3675 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3) 3676 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7) 3678 BIT(11) 3681 #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3) 3685 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0) 3686 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1) 3687 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT( [all...] |
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ |
H A D | ath.h | 31 #define BIT(nr) (1UL << (nr)) macro 149 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 150 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
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