a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (c) 2008-2011 Atheros Communications Inc.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Original from Linux kernel 3.0.1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Permission to use, copy, modify, and/or distribute this software for any
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * purpose with or without fee is hereby granted, provided that the above
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * copyright notice and this permission notice appear in all copies.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "Unable to read eeprom region\n");
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "Reading from EEPROM, not flash\n");
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "Invalid EEPROM Magic. Endianness mismatch.\n");
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync el = swab16(ah->eeprom.map4k.baseEepHeader.length);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < el; i++)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "EEPROM Endianness is not native.. Changing\n");
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync word = swab16(eep->baseEepHeader.blueToothOptions);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync integer = swab32(eep->modalHeader.antCtrlChain[i]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync word = swab16(eep->modalHeader.spurChans[i].spurChan);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG("ath9k: Bad EEPROM checksum 0x%x or revision 0x%04x\n",
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct modal_eep_4k_header *pModal = &eep->modalHeader;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct base_eep_header_4k *pBase = &eep->baseEepHeader;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (i != 0)) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (j = 0; j < 32; j++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC (%d,%4x): %4.4x %8.8x\n",
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC: Chain %d | "
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC %3d Value %3d | "
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC %3d Value %3d | "
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC %3d Value %3d | "
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "PDADC %3d Value %3d |\n",
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int i;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync 0, { 0, 0, 0, 0}
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync 0, { 0, 0, 0, 0 }
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync 0, {0, 0, 0, 0}
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync twiceLargestAntenna = (int16_t)min(AntennaReduction -
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int i;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Update regulatory */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < Ar5416RateSize; i++)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* OFDM power per rate */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* CCK power per rate */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* HT20 power per rate */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* HT40 power per rate */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void ath9k_hw_4k_set_addac(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set the block 1 value to block 0 value */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Read EEPROM header info and program the device for correct operation
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * given the channel value.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct base_eep_header_4k *pBase = &eep->baseEepHeader;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Single chain for 4K EEPROM*/
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Initialize Ant Diversity settings from EEPROM */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < 5; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, int is2GHz)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync "Getting spur idx:%d is2Ghz:%d val:%x\n",