Lines Matching refs:BIT
923 #define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3)
3465 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11)
3642 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3)
3675 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3)
3676 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7)
3678 BIT(11)
3681 #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3)
3685 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0)
3686 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1)
3687 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT(2)
3688 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT BIT(3)
3689 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT BIT(4)
3690 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT BIT(5)
3691 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT BIT(6)
3692 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT BIT(7)
3693 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT BIT(8)
3694 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT BIT(9)
3695 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT BIT(10)
3696 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT BIT(11)
3697 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT BIT(12)
3698 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT BIT(13)
3699 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT BIT(14)
3700 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT BIT(15)
3701 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT BIT(16)
3710 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG BIT(0)
3723 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT BIT(0)
3724 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT BIT(3)
3725 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT BIT(7)
3729 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0)
3730 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3)
3731 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT BIT(7)
3738 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR BIT(3)
3739 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR BIT(7)
3740 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR BIT(11)
3741 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15)
3742 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET BIT(19)
3743 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS BIT(23)
3747 #define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM BIT(3)
3759 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN BIT(19)
3760 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN BIT(23)
3761 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN BIT(27)
3762 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN BIT(31)
3763 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN BIT(35)
3764 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN BIT(39)
3771 #define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK BIT(0)
3773 #define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK BIT(0)
3775 #define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT BIT(0)
3777 #define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG BIT(7)
3779 #define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7)
3783 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK BIT(3)
3784 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR BIT(7)
3788 #define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT BIT(3)
3791 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3)
3792 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK BIT(7)
3794 BIT(11)
3795 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED BIT(15)
3810 BIT(0)
3812 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START BIT(0)
3813 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END BIT(1)
3814 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START BIT(2)
3815 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END BIT(3)
3816 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START BIT(4)
3817 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END BIT(5)
3818 #define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN BIT(6)
3819 #define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN BIT(7)
3820 #define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8)
3821 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START BIT(9)
3822 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END BIT(10)
3823 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START BIT(11)
3824 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END BIT(12)
3825 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START BIT(13)
3826 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END BIT(14)
3827 #define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN BIT(15)
3828 #define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN BIT(16)
3829 #define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17)
3830 #define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19)