Searched refs:lane (Results 1 - 4 of 4) sorted by relevance
| /solaris-x11-s11/open-src/kernel/drm/src/ |
| H A D | drm_dp_helper.c | 38 int lane)
40 int i = DP_LANE0_1_STATUS + (lane >> 1);
41 int s = (lane & 1) * 4;
51 int lane; local
57 for (lane = 0; lane < lane_count; lane++) {
58 lane_status = dp_get_lane_status(link_status, lane);
68 int lane; local
71 for (lane
37 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
79 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
91 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
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| /solaris-x11-s11/open-src/kernel/sys/drm/ |
| H A D | drm_dp_helper.h | 347 int lane);
349 int lane);
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| /solaris-x11-s11/open-src/kernel/i915/src/ |
| H A D | intel_dp.c | 100 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
716 DRM_DEBUG_KMS("DP link computation with max lane count %i "
765 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1483 /* Program Tx lane resets to default */
1725 int lane; local
1729 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1730 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1731 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
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| H A D | intel_display.c | 3955 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3980 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3989 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4013 int lane, link_bw, fdi_dotclock; local
4021 * Hence the bw of each lane in terms of the mode signal
4030 lane = i915_default_lanes;
4032 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4035 pipe_config->fdi_lanes = lane;
4037 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
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