Searched refs:xge_assert (Results 1 - 19 of 19) sorted by relevance

/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxge-list.h66 xge_assert(header != NULL);
81 xge_assert(header != NULL);
82 xge_assert(header->next != NULL);
83 xge_assert(header->prev != NULL);
100 xge_assert(item != NULL);
101 xge_assert(item->next != NULL);
102 xge_assert(item->prev != NULL);
123 xge_assert(new_item != NULL);
124 xge_assert(prev_item != NULL);
125 xge_assert(prev_ite
[all...]
H A Dxgehal-mm.h105 xge_assert(memblock);
108 xge_assert(offset >= 0 && offset < mempool->memblock_size);
111 xge_assert((*memblock_item_idx) < mempool->items_per_memblock);
134 xge_assert(mempool->memblocks_arr[memblock_idx]);
H A Dxge-debug.h391 * xge_assert
400 #define xge_assert(test) { \ macro
404 #define xge_assert(test) macro
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-driver.c129 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, adapter_status) ==
131 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, tx_traffic_int) ==
133 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, dtx_control) ==
135 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, tx_fifo_partition_0) ==
137 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, pcc_enable) ==
139 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, prc_rxd0_n[0]) ==
141 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, rti_command_mem) ==
143 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mac_cfg) ==
145 xge_assert(xge_offsetof(xge_hal_pci_bar0_t, rmac_addr_cmd_mem) ==
147 xge_assert(xge_offseto
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H A Dxgehal-channel.c88 xge_assert(rxdp->host_control!=0);
105 xge_assert(post_qid + 1 >= XGE_HAL_MIN_FIFO_NUM &&
110 xge_assert(post_qid + 1 >= XGE_HAL_MIN_RING_NUM &&
115 xge_assert(size);
143 xge_assert(channel->pdev);
157 xge_assert(size);
231 xge_assert(channel->pdev);
306 xge_assert(device);
307 xge_assert(attr);
328 xge_assert((channe
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H A Dxgehal-fifo-fp.c34 xge_assert(txdp);
38 xge_assert(txdl_priv);
39 xge_assert(txdl_priv->dma_object);
40 xge_assert(txdl_priv->dma_addr);
42 xge_assert(txdl_priv->dma_object->handle == txdl_priv->dma_handle);
139 xge_assert(invalid_frags == 0);
151 xge_assert(frags);
164 xge_assert(frags == 0)
175 xge_assert(((xge_hal_channel_t *)channelh)->reserve_length +
180 xge_assert(
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H A Dxgehal-ring.c85 xge_assert(from_item);
90 xge_assert(to_item);
132 xge_assert(item);
133 xge_assert(ring);
172 xge_assert(memblock_index <= 0xFFFF);
173 xge_assert(i <= 0xFFFF);
218 xge_assert(status == XGE_HAL_OK);
257 xge_assert(queue->configured);
315 xge_assert(ring->reserved_rxds_arr[0] ==
353 xge_assert(rin
[all...]
H A Dxgehal-ring-fp.c35 xge_assert(rxdp);
38 xge_assert(ring);
57 xge_assert(rxd_priv);
58 xge_assert(rxd_priv->dma_object);
60 xge_assert(rxd_priv->dma_object->handle == rxd_priv->dma_handle);
62 xge_assert(rxd_priv->dma_object->addr + rxd_priv->dma_offset ==
516 xge_assert((char *)prev_dtrh +
706 xge_assert(((xge_hal_ring_rxd_5_t *)
712 xge_assert(rxdp->host_control!=0);
721 xge_assert(*t_cod
[all...]
H A Dxge-queue.c100 xge_assert(queue->tail_ptr >= queue->head_ptr);
101 xge_assert(queue->tail_ptr >= queue->start_ptr &&
103 xge_assert(queue->head_ptr >= queue->start_ptr &&
147 xge_assert(real_size <= XGE_QUEUE_BUF_SIZE);
215 xge_assert(queue->tail_ptr >= queue->head_ptr);
216 xge_assert(queue->tail_ptr >= queue->start_ptr &&
218 xge_assert(queue->head_ptr >= queue->start_ptr &&
348 xge_assert(!xge_list_is_empty(&queue->list_head));
H A Dxgehal-channel-fp.c142 xge_assert(channel->work_arr[channel->post_index] == NULL);
156 xge_assert(channel->work_arr);
157 xge_assert(channel->compl_index < channel->length);
H A Dxgehal-fifo.c42 xge_assert(item);
48 xge_assert(txdl_priv);
113 xge_assert(item);
120 xge_assert(txdl_priv);
289 xge_assert(fifo->channel.reserve_length);
293 xge_assert(max_arr_index);
527 xge_assert(txdp);
H A Dxgehal-stats.c42 xge_assert(!stats->is_initialized);
220 xge_assert(stats->hw_info);
223 xge_assert(hldev);
252 xge_assert(stats->hw_info);
255 xge_assert(hldev);
256 xge_assert(stats->is_initialized);
312 xge_assert(stats->hw_info);
315 xge_assert(hldev);
714 xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN)
779 xge_assert(xge_hal_device_check_i
[all...]
H A Dxgehal-mm.c359 xge_assert(mempool->memblocks_arr[i]);
360 xge_assert(mempool->memblocks_dma_arr + i);
H A Dxgehal-device.c73 xge_assert(((xge_hal_device_t*)data)->magic == XGE_HAL_MAGIC);
545 xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC);
1319 xge_assert(default_dtx_cfg);
2060 xge_assert(((spdm_bar_num != 0) && (spdm_bar_num != 1)));
4295 xge_assert(!hldev->stats.is_enabled);
4787 xge_assert(hldev);
4826 xge_assert(hldev);
5200 xge_assert(hldev->regh0);
5201 xge_assert(hldev->regh1);
5202 xge_assert(hlde
[all...]
H A Dxgehal-device-fp.c81 xge_assert(bar0);
94 xge_assert(isrbar0);
112 xge_assert(bar1);
113 xge_assert(fifo);
H A Dxgehal-mgmt.c254 xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN);
293 xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN);
336 xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN);
377 xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN);
H A Dxgehal-mgmtaux.c38 xge_assert(retsize < bufsize); \
1407 xge_assert(hldev->dump_buf != NULL);
/illumos-gate/usr/src/uts/common/io/xge/drv/
H A Dxgell.c204 xge_assert(mutex_owned(&bf_pool->pool_lock));
208 xge_assert(bf_pool->head);
215 xge_assert(rx_buffer->dma_addr);
239 xge_assert(mutex_owned(&bf_pool->pool_lock));
440 xge_assert(rx_buffer != NULL);
459 xge_assert(!mutex_owned(&bf_pool->pool_lock));
545 xge_assert(rx_buffer);
546 xge_assert(rx_buffer->dma_addr);
731 xge_assert(dma_data == rx_buffer->dma_addr);
916 xge_assert(txd_pri
[all...]
H A Dxge.c888 xge_assert(lldev->intr_table != NULL);
1051 xge_assert(lldev->intr_table != NULL);

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