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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Daeu_inputs.h49 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION0 (0x1<<0)// Type: Event, Required Destination: MCP/Driver0
50 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION1 (0x1<<1)// Type: Event, Required Destination: MCP/Driver1
51 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)// Type: Event, Required Destination: MCP
52 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_0 (0x1<<3)// Type: Event, Required Destination: MCP
53 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_0 (0x1<<4)// Type: Event, Required Destination: MCP
54 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)// Type: Event, Required Destination: MCP
55 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_1 (0x1<<6)// Type: Event, Required Destination: MCP
56 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_1 (0x1<<7)// Type: Event, Required Destination: MCP
57 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_1 (0x1<<8)// Type: Event, Required Destination: MCP
58 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<
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H A Dmisc_bits.h4 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
5 #define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
6 #define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
7 #define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
8 #define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
9 #define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
10 #define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
11 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
12 #define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
13 #define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<
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H A D57712_reg.h4 #define ATC_REG_ATC_1_WAY 0x110004UL //ACCESS:RW DataWidth:0x1 Description: If set the ATC will use only one way per set
7 #define ATC_REG_ATC_WAIT_IF_MISS 0x110010UL //ACCESS:RW DataWidth:0x1 Description: WaitIfMiss configuration bit
8 #define ATC_REG_ATC_WAIT_IF_PENDING 0x110014UL //ACCESS:RW DataWidth:0x1 Description: WaitTransPending cofiguration bit
21 #define ATC_REG_ATC_DISABLE_BYPASS 0x110048UL //ACCESS:RW DataWidth:0x1 Description: disables the bypass on the GPA table
22 #define ATC_REG_ATC_ISSUE_4_CYCLES 0x11004cUL //ACCESS:RW DataWidth:0x1 Description: Issue event once in four cycles (instead of 2)
25 #define ATC_REG_ATC_PIGGYBACKED_TREQ_EN 0x110058UL //ACCESS:RW DataWidth:0x1 Description: Piggybacked treq issue enabled
26 #define ATC_REG_ATC_WAIT_RESP 0x11005cUL //ACCESS:RW DataWidth:0x1 Description: Allows the ATC to return Wait response
35 #define ATC_REG_ATC_CHECK_TAGS 0x110080UL //ACCESS:RW DataWidth:0x1 Description: CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ
38 #define ATC_REG_ATC_DIS_MLKP 0x11008cUL //ACCESS:RW DataWidth:0x1 Description: Disables the main lookup interface
39 #define ATC_REG_ATC_DIS_PLKP 0x110090UL //ACCESS:RW DataWidth:0x1 Descriptio
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H A Digu_def.h72 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
73 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
74 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
75 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
76 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
77 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
80 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
81 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
84 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
95 #define IGU_FID_ENCODE_IS_PF (0x1<<
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/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Data.conf37 ata-options=0x1;
42 drive0_block_factor=0x1;
43 drive1_block_factor=0x1;
/illumos-gate/usr/src/lib/libm/common/Q/
H A Dfmodl.c61 unsigned x1, x2, x3, y1, y2, y3, z1, z2, z3; local
64 x1 = __H1(x);
94 x0 = x1 >> 16;
95 x1 = (x1 << 16) | (x2 >> 16);
101 x0 = (x0 << 1) | (x1 >> 31);
102 x1 = (x1 << 1) | (x2 >> 31);
138 x0 = x1 >> 16;
139 x1
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/illumos-gate/usr/src/boot/sys/boot/i386/libfirewire/
H A Dfwohcireg.h157 #define OHCI_SPD_S200 0x1
188 #define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
190 #define OHCI_CNTL_BUFFIL (0x1 << 31)
191 #define OHCI_CNTL_ISOHDR (0x1 << 30)
192 #define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
193 #define OHCI_CNTL_MULTICH (0x1 << 28)
195 #define OHCI_CNTL_DMA_RUN (0x1 << 15)
196 #define OHCI_CNTL_DMA_WAKE (0x1 << 12)
197 #define OHCI_CNTL_DMA_DEAD (0x1 << 11)
198 #define OHCI_CNTL_DMA_ACTIVE (0x1 << 1
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/illumos-gate/usr/src/uts/sun4v/sys/
H A Dfault_iso.h38 #define FMA_CPU_REQ_OFFLINE 0x1
49 #define FMA_CPU_RESP_FAILURE 0x1
53 #define FMA_CPU_STAT_OFFLINE 0x1
64 #define FMA_MEM_REQ_RETIRE 0x1
77 #define FMA_MEM_RESP_FAILURE 0x1
81 #define FMA_MEM_STAT_RETIRED 0x1
H A Dvldc.h44 #define VLDC_IOCTL_OPT_OP (VLDC_IOCTL | 0x1) /* ctrl op */
49 #define VLDC_OP_GET 0x1 /* get specified value */
53 #define VLDC_OPT_MTU_SZ 0x1 /* MTU */
58 #define VLDC_PORT_CLOSED 0x1 /* port is closed */
/illumos-gate/usr/src/uts/common/sys/contract/
H A Ddevice.h43 #define CT_DEV_EV_ONLINE 0x1 /* device is moving to online state */
51 #define CTDP_ACCEPT 0x1 /* the acceptable set term */
57 #define CTDP_NONEG_SET 0x1 /* set noneg */
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_82543.h40 #define PHY_SOF 0x1
42 #define PHY_OP_WRITE 0x1
45 #define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */
/illumos-gate/usr/src/cmd/sgs/libcrle/common/
H A D_crle.h38 #define CRLE_AUD_DEPENDS 0x1 /* Audit - collect dependencies */
/illumos-gate/usr/src/uts/common/sys/
H A Dsysdc.h37 #define SYSDC_THREAD_BATCH 0x1 /* thread does batch processing */
H A Dagpgart.h113 #define AGPSTAT_SBA (0x1 << 9) /* always 1 for 3.0 */
114 #define AGPSTAT_OVER4G (0x1 << 5)
115 #define AGPSTAT_FW (0x1 << 4)
118 #define AGP2_RATE_1X 0x1
124 #define AGPSTAT_GART64B (0x1 << 7) /* target only */
125 #define AGPSTAT_MODE3 (0x1 << 3)
127 #define AGP3_RATE_4X 0x1
132 #define AGPCMD_SBAEN (0x1 << 9) /* must be 1 for 3.0 */
133 #define AGPCMD_AGPEN (0x1 << 8)
134 #define AGPCMD_OVER4GEN (0x1 <<
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/illumos-gate/usr/src/boot/sys/boot/fdt/dts/powerpc/
H A Dmpc8572ds.dts101 reg = <0x1>;
421 reg = <0x1>;
631 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
632 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
633 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
634 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
637 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
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H A Dmpc8555cds.dts112 0x1 0x0 0xff000000 0x00800000
128 reg = <0x1 0x0 0x00800000>;
262 reg = <0x1>;
355 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
356 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
357 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
358 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
361 0x8800 0x0 0x0 0x1
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/illumos-gate/usr/src/lib/libm/common/m9x/
H A Dremquol.c63 unsigned x1, x2, x3, y1, y2, y3, z1, z2, z3; local
66 x1 = __H1(x);
95 x0 = x1 >> 16;
96 x1 = (x1 << 16) | (x2 >> 16);
102 x0 = (x0 << 1) | (x1 >> 31);
103 x1 = (x1 << 1) | (x2 >> 31);
142 x0 = x1 >> 16;
143 x1
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/illumos-gate/usr/src/uts/common/sys/sata/adapters/ahci/
H A Dahcireg.h61 #define AHCI_HBA_CAP_SXS (0x1 << 5) /* external SATA */
62 #define AHCI_HBA_CAP_EMS (0x1 << 6) /* enclosure management */
63 #define AHCI_HBA_CAP_CCCS (0x1 << 7) /* command completed coalescing */
65 #define AHCI_HBA_CAP_PSC (0x1 << 13) /* partial state capable */
66 #define AHCI_HBA_CAP_SSC (0x1 << 14) /* slumber state capable */
67 #define AHCI_HBA_CAP_PMD (0x1 << 15) /* PIO multiple DRQ block */
68 #define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */
69 #define AHCI_HBA_CAP_SPM (0x1 << 17) /* port multiplier */
70 #define AHCI_HBA_CAP_SAM (0x1 << 18) /* AHCI mode only */
71 #define AHCI_HBA_CAP_SNZO (0x1 << 1
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/illumos-gate/usr/src/uts/intel/io/
H A Dbscv.conf38 reg=0x0, 0x0, 0x4000, 0x201, 0x0, 0x1;
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dmv88x201x.c42 * register. mmd(0x1) addr(0x7)
51 #define LINK_ENABLE_BIT 0x1
53 (void) mdio_read(cphy, 0x1, 0x7, &led);
57 (void) mdio_write(cphy, 0x1, 0x7, led);
60 (void) mdio_write(cphy, 0x1, 0x7, led);
78 (void) mdio_write(cphy, 0x1, 0x9002, 0x1);
94 (void) mdio_write(cphy, 0x1, 0x9002, 0x0);
114 (void) mdio_read(cphy, 0x1, 0x9003, &val);
115 (void) mdio_read(cphy, 0x1,
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D5710_hsi.h35 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
37 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
39 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
41 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
43 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) /* BitField agg_vars1Various aggregative variables ULP Rx SE counter flag enable */
45 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) /* BitField agg_vars1Various aggregative variables ULP Rx invalidate counter flag enable */
51 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) /* BitField agg_vars1Various aggregative variables Enable decision rule for fin_received_cf */
53 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 1 */
55 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 2 */
57 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<2
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/illumos-gate/usr/src/uts/sun4u/starcat/sys/
H A Dschpc_msg.h121 #define PCIMSG_GETSLOTSTATUS 0x1
133 #define PCIMSG_SLOTCOND_GOOD 0x1
142 #define PCIMSG_FREQ_66MHZ 0x1
151 #define PCIMSG_MODE_PCIX 0x1
157 #define PCIMSG_PRSNT_25W 0x1
164 #define PCIMSG_ON 0x1
179 #define PCIMSG_REPLY_FAIL 0x1
/illumos-gate/usr/src/lib/libbc/inc/include/sys/
H A Dmman.h41 #define PROT_READ 0x1 /* pages can be read */
88 #define MS_ASYNC 0x1 /* return immediately */
100 #define MCL_CURRENT 0x1 /* lock current mappings */
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_fm.h57 #define PX_FABRIC_SCAN (0x1 << 6)
58 #define PX_HW_RESET (0x1 << 5)
59 #define PX_PANIC (0x1 << 4)
60 #define PX_EXPECTED (0x1 << 3)
61 #define PX_PROTECTED (0x1 << 2)
62 #define PX_NO_PANIC (0x1 << 1)
63 #define PX_NO_ERROR (0x1 << 0)
65 #define PX_HB (0x1 << 2)
66 #define PX_RP (0x1 << 1)
67 #define PX_RC (0x1 <<
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/illumos-gate/usr/src/cmd/sgs/rtld.4.x/
H A Drtsubrs.c56 va_list x1; local
58 va_start(x1);
59 prf(stdout, fmt, x1);
60 va_end(x1);
72 va_list x1; local
74 va_start(x1);
75 prf(fd, fmt, x1);
76 va_end(x1);
87 va_list x1; local
90 va_start(x1);
108 va_list x1; local
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